MadeEasy Test Series: CO & Architecture - Addressing Modes

Question

The Data transfer instruction size is $64-bit$ ALU, ALU operation instruction size is $32-bit$ and branch instruction size is $16-bit$. Assume program has been loaded in the memory starting from address 3000 decimal. If an interrupt occurs during the execution of $I-6$, the return address pushed onto the stack is:

Doubt: When $I-6$ is executing, PC value will be 3030, but given answer is 3028

Previous Q: https://gateoverflow.in/1058/gate2004-63

Comments

return address will be 3030.

I too think halt must have some size. As it is instruction and it must contains code in binary that tells processor what to do when it sees halt.

But anyway return address will be address following halt.

Explanation given in link you shared

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The question gate overflow question states after halt execution, in this case it's during the execution

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according to this link https://www.tutorialspoint.com/hlt-instruction-in-8085,

it will be 3030.

Answer 1

Instrn(Instruction)

Answer 2

At the time I6 is fetched from memory to Instruction register...the value of PC is updated to 330(ie address of next instruction).

PC= 328+2= 330

now during the execution of I6 interrupt occurs, which will be serviced after the execution of I6 completed.

Now we need to know how halt instruction works internally.. It changes the value of PC(program counter) to the address of current instruction. (That's why the system gets blocked as it keeps executing the current instruction again and again..) so the value of PC changes to 328 ..which will be pushed onto the stack.

Pc= 328

Hence after the interrupt has been serviced, halt instruction execution restarts.

Answer 3

I1: 3000-3007 (Data Transfer 8B)

I2:3008-3011   (ALU B)

I3:3012-3015   (ALU 4B)

I4;3016-3023 (Data Transfer 8B)

I5:3024-3027 (ALU )

I6:3028-3029 (Branch)

Halt operation leads to unconditional loop therefore PC points to same location.

So, After execution of HALT PC will contain 3028