Therefore , to transfer 16 bytes cycles needed = 16*2=32 cycles , So total cycles needed is 32+10 = 42 cycles
@Sanandan Are all 16 bytes transferred at once? considering the fact that DMA is using cyle stealing.
In the question, it is mentioned “ The DMA controller requires 10 cycles for initialization of operation and transfer takes 2 cycles to transfer one byte of data from the device to the memory.” So if I read this specific part of the question as – a DMA controller requires “10 cycles for initialization of operation and transfer takes 2 cycles” to transfer one byte of data from the device to the memory, then will it not be feasible with the concept of DMA cycle stealing as mentioned in this Direct memory Access pdf?.
If read like this then the calculation will be like 10+2 = 12 cycle for 1 byte, CPU will only be blocked during transfer time i.e. for 1 byte of data being transferred CPU will be blocked and it will take (12 * 2.5) micro-second = 30 micro-second.
(cycle time = 2.5 micro-second, As device transfer rate is 1KBps so 1 byte = 1000 mico-second and for 16 byte data preparation time is = 16 * 1000 micro-second = 16000 micro-second.
So percentage of processor time blocked during this DMA operation = (30/16000) * 100 = 0.1875.
But its not always true that a transfer of 1B takes place in cycle stealing.
@MiNiPanda you are right, In this → Question transfer of 8 bytes takes place but here is the catch, in this Question it has been mentioned that 1 word = 8 bytes(or 64 bit), so in the case of the current question, should we assume that 16 bytes = 1 word?.
In this question, it has also not been said that in cycle stealing mode whenever 16 bytes of data are available in the buffer it will be transferred to the main memory, unlike this Question
Seems the question is badly framed.
@Bikram 1 sir or anyone, please help with this question, what is the correct answer and correct way to understand.