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VIRTUAL GATE TEST SERIES
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Ajay Maurya 6
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CO and Architecture
Jan 10, 2019
closed
Jan 11, 2019
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Ajay Maurya 6
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closed as a duplicate of:
GATE CSE 2006 | Question: 80
cache-memory
Ajay Maurya 6
asked
in
CO and Architecture
Jan 10, 2019
closed
Jan 11, 2019
by
Ajay Maurya 6
by
Ajay Maurya 6
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Jan 11, 2019
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Virtual Gate Test Series: CO & Architecture - Cache Access
my question is even in case of a miss the cache will still be accessed and then main memory, right? please explain this when to consider higher memory level access time and when not to consider it
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khushtak
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Virtual Gate Test Series: CO & Architecture - Cache Memory
Consider a $256k$ $4$- way set associative cache with block size $64$ Bytes. Main memory is $2Gb.$ The number of bits used for tag,set and word will be respectively? $10,15,6$ $9,16,6$ $8,17,6$ $7,18,6$ I think answer is $15,10,6 $ $\text{(tag,set,word)}$
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Balaji Jegan
asked
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Jan 15, 2018
472
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Virtual GATE question
Balaji Jegan
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Jan 15, 2018
by
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472
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cache-memory
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4
srestha
asked
in
Operating System
Jul 18, 2018
241
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Virtual Memory Access Time
Avg. virtual address access time = avg address translation time+avg. memory access time Why do we need address translation time separately?(otherwise we do TLB access, then cache access then MM access) Avg address translation time=TLB access time+page table access ... question is if TLB hit is taking then why do we take cache hit? We take cache hit, when TLB miss right?
srestha
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in
Operating System
Jul 18, 2018
by
srestha
241
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