GATE CSE 2004 | Question: 47

Question

Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is $90$%, and the page fault rate is one in every $10,000$ instructions. What is the effective average instruction execution time?

• A. $\text{645 nanoseconds}$
• B. $\text{1050 nanoseconds}$
• C. $\text{1215 nanoseconds}$
• D. $\text{1230 nanoseconds}$

Comments

@anurags228

bro how u got 450 ?

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Everyone is giving different answers. Literally confused. Someone pls say which one is the correct solution to this question.

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Instead of 2*( Effective average Instruction execution time )

if i take 100  + 1*( Effective average Instruction execution time )

then im getting 1215 ns sec as my answer

and that is even matching with options too.

Answer 1

Average Instruction execution time

 = Average CPU execution time + Average time for getting data(instruction operands from memory for each instruction)

 =   Average CPU execution time
   + Average address translation time for each instruction
   + Average memory fetch time for each instruction
   + Average page fault time for each instruction

 $=\underbrace{100}_{\text{Average CPU execution time}}+\underbrace{2\left(0.9 (0) + 0.1 (2 \times 150)\right)}_{\text{Average address translation time for each instruction}} + \underbrace{2\times 150}_{\text{Average memory fetch time for each instruction}} + \underbrace{\dfrac{1}{10000} \times 8 \times 10^6}_{\text{Average page fault time for each instruction}}$

(Page Fault Rate per 10,000 instruction is directly given in question. Two memory accesses per instruction and  hence we need 2 $\times$ address translation time for average instruction execution time)

[ TLB access time assumed as 0 and 2 page tables need to be accessed in case of TLB miss as the system uses two-level paging ]

= $100 + 60 + 300 + 800$

= $1260 \textsf{ ns}$

PS: GATE question might have missed the time for second address translation in their calculation which might have made them give 1230 in option D instead of 1260.

Comments

Since we have a TLB, should we not only get page fault when its a TLB miss?

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That is true. But in the question it is said,

"the page fault rate is one in every 10,000 instructions"

So, the page fault rate given should be based on just instructions and not on page accesses. 

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I think I have a problem in understanding here. Is average memory fetch here, is what we usually count when we fetch an instruction from memory after its corresponding frame is located, before it is executed?

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Instruction execution time = CPU time + Memory acess time
Memory access time = Time for instruction fetch + Time for getting data
Time for getting either data or instruction from memory = address translation time + memory access time + page fault time if any.

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Thanks :)

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It should be 8*1000000

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Corrected. Thanks for that :)

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I would say that's a rather unconventional interpretation of the problem yet with the right answer.
There are a few questions:
1. If this is a standard interpretation, then I have not been able to spot this anywhere before this question and then this post.
2. How is Average Address Translation ((0.9 * 0) + 0.1 * (2 * 150)) interpretation formalized?

We know that in the presence of a TLB, it is a(c+m) + (1-a)(c+3m).. where does this fit in here?

2 page tables needs to be accessed in case of TLB miss
Where is this information used in the equation. If it is 0.1*(2*150) then I think that should be 0.1*150.. Is it a per instruction TLB hit/miss or per mem. access?

Please help me clear the air. Thanks!

EDIT>> The doubts are resolved in the discussion here.. 

https://www.facebook.com/groups/core.cs/permalink/894263637272557/

Appreciate everybody's help!

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"We know that in the presence of a TLB, it is a(c+m) + (1-a)(c+3m).. where does this fit in here?"

Is this a standard formula? If so please give a reference.

2 page tables are accesses in case of TLB miss -> yes, this corresponds to 0.1 * 2 * 150. Why it should be 0.1*150?

TLB hit should be for every memory access. So, in the address translation time *2 must be there giving 60ns instead of 30ns, since each instruction has 2 memory accesses. 

@Suraj 1260ns should be the answer rt?

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Arjun Sir , u considered TLB access time to be 0 thats fine. but when the tlb is accesed it only gets a refrerence of where the page frame is in the memory...so it has to use the memory access time too multiplying with .90 factor to retrive the data...

Plz correct where am going wrong.

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@Riya-Roy I considered address translation time and memory access time separately. The memory access time of (2*150) is common for TLB hit as well as TLB miss. So, I put that as separate. You can include that inside TLB hit and TLB miss calculation and then also answer will be same.

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Actually, Page fault service time includes the time taken for unsuccessfully searching the paging table(page fault overhead ). So, The average memory access time is to be multiplied by (1-.0001) . But that would change the answer only within few decimal precision[very insignificant].
I say this because you will find the following in every book.
Effective Access Time (EAT)
 EAT = (1 – p) x memory access +
             p (page fault overhead + [swap page out ] + swap page in + restart overhead)

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@arjun sir why you didn't multiply 2 to average fault time

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page fault rate per 10,000 instruction

So, this is per instruction and not per memory access. 

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but sir in question they are saying An average instruction takes 100 nanoseconds of CPU time, and two memory accesses.

here memory access means effective memory access time then

effective average instruction execution time=100+2(EMA)

then in EMA page fault service is also included therefore all factor will be multiply by 2.

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No. Thats not the correct way. Because page fault rate is per instruction. So, even if an instruction has say 5 memory access and each of them can cause page fault, we need not bother about that. The given page fault per instruction has already counted that, and that is the significance of 

per instruction

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got your point sir....

what is the wrong in this answer:-

1. Average Instruction execution time
2. = Average CPU execution time + Average memory access time for each instruction
3. = Average CPU execution time + Average address translation time + Average memory fetch for each instruction + Average page fault time for each instruction
4. = 100 + ((0.9 * 0) + 0.1 * (2 * 150)) + 2*150 + (1/10000) * 8 * 1000
5. [ TLB access time assumed as 0 and 2 page tables needs to be accessed in case of TLB miss as the system uses two-level paging]
6. = 100 + 30 + 300 + 800
7. = 1230 ns

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1.CPU excecution time was given.....next when we find the page table entry(PTE) in TLB we immediately go to that corresponding page in main memory and get the instruction.TLB acess time was not given so just ignore it.
2.When we dont find in TLB then we go to page table(2 levels as it was given in question) and then to main memory.Also he said that it takes 2 regular memory acesses on average(i repeat the term here "average") for every instruction.So when there is TLB Hit or TLB miss we have 2 regular memory access but not 1 memory access and it was 2 level paging scheme in the case of TLB miss.we need to consider here 2 memory access(just like indirect addressing mode).
3.Then comes the page fault,and it was said page fault probability is one in 10000 instructions.And page fault service time was given for that.
4. Now putting all the terms together and going from top tp bottom .....

EAIET(i am sorry here for using the acronym)=[CPU execution time]+(TLB Hit*2*Memory access time +TLB miss ratio(page table access time+2*memory access time ))+{page fault probability*page fault service time}
That is 100ns+(0.9*2*150+0.1(150+150+2*150))+800ns.....[800ns herecomes from 0.0001*8*10^6]

=100ns+2*(135+30)ns+800ns
=100ns+2*165ns+800ns
=1230ns
 

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Yes. But we have two memory access per instruction. Say like below

Add R, @1000, @2000

where 1000 and 2000 are memory addresses. Now, both 1000 and 2000 must be translated to physical address. So, 2 times address translation time must be counted.

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but if we consider locality of reference property of the program,the other memory reference will be made from the same page,whose translation is saved into the TLB.
then we need not calculate address translation again.

This is how I am calculating: 
 

Out of 10000 instructions, 9000 instructions, i.e. 90%, will have a TLB hit and 1000 instructions will have TLB miss. Out of 1000, 1 instruction will page fault. 

For TLB hit = (Execution time + First memory access + Second memory access) = (100 + 150 + 150) nanosecond = 400 nanosecond

For TLB miss = Execution time  + (First page table lookup time for first memory access + Second page table lookup time for first memory access + First memory access) + (First page table lookup time for second memory access + Second page table lookup time for second memory access + Second memory access) = (100 + 150 + 150 + 150 + 0 + 0 + 150) nanosecond = 700 nanosecond

Average execution time= (9000*400+1000*700+8*1000000)/10000 nanosecond = 1230 nanosecond

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@Ajit If we assume 100% locality of reference for the memory accesses within each instruction, that is correct. But I don't think we can take that assumption as it can't be real. Anyway 1230 is the only choice possible and even if the answer is 1260, we should write 1230 for GATE if 1260 is not in choice.

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@csegate That is wrong. Page fault rate is given directly and is with respect to No. of instructions and not with respect to number of memory accesses. We should follow the question.  

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sir why are you not consider effective average instruction execution time== CPU TIME + 2 (effective memory access time )

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^That is what I considered. Just that memory access time involved other factors. Question should have put "effective memory access time per instruction" and our life could have been much simpler.

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Sir, you have explained it beautifully....

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@Arjun Sir , u have calculated 1/10000 as page fault service time.

But why u have not calculated separately 9999/10000 as no page fault.

plz tell. How getting this formula for calculation.

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@srestha Because I'm too bad in mathematics :) I just missed it. Or I intentionally made my life simpler. If we include that - then one more thing - does page fault service time include memory access time?

Now, you can try calculating the answer with any of the above assumtpions and still the answer will be within 1259-1261. So, for the sake of smplicity we can ignore them.

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Sir, can you please explain how my equation differs from yours?

My equation is this:

EMAT=

100 + 2 (0.9(150) + 0.1(300)) +800

=1230ns

90% of times CPU will directly go to main memory ie 0.9*150

10% of times CPU will go to page table hence 0.1*(150+150)

and as mentioned 2 memory accesses are required so 2*(addition of above two equations)

avg page fault (800ns) is added and +100ns for CPU access time.

Did I miss anything here ?

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Average address translation time for each instruction = 2(0.9(0)+0.1(2×150))

why 2 is multipled

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sry got it . here he said 2 memeory aceess.

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@Nitesh, @Anirudh

Each instrucion is having 2 memory references. And each of them must have its VA to PA translated. i.e., each instruction causes 2 TLB look-up.

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Got it sir. 

An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. missed bold part .

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This question won't come again for GATE. But it is quite important as it shows how each word in the question must be interpreted correctly. Even for someone working in architecture area, this problem is not easy to solve first time - because understanding what the question setter meant takes time. So, having solved some question like these before GATE will really help in others.

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Hi Arjun Sir,

Here do we need to make two memory access to translate VA to PA(apart from 2 paging scheme).

CPU execution=100

VA to PA= 0+2*0.1*150=30  Since TLB time is zero and 2 level paging.

Effective Memory access= 2* 150 +(8*10^6)/10000=1100 ( Since an avg instruction takes 2 memory access)

So total=(100+30+1100)=1230

Please tell me sir why I need to multily again 2 while VA to PA time calculation as here I presume that to execute an instruction I need two memory access but not the address translation (apart from 2 memory access for 2 level pagaing).

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2 memory access means 2 VA to PA translation and for each we need to see page tables (supposing TLB miss) and page tables are in memory.

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In the last line, don't you think it should be (8*10⁶ *0.1 /10⁴) . So 80 + 30 + 150=260 I guess.

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@Arjun its given a 2 level paging scheme so 2 memory access for Page Tables then 1 memory access for frame that holds the instruction o total 3 right?

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@Nitesh

EMAT=

100 + 2 (0.9(150) + 0.1(450)) +800

=1260ns
 

450 because 2 memory accesses for the page table page and one more for accessing the page required.

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@arjun sir if we consider no page fault rate then 0.9999*150=149.98ns get added to result.....so why u have said answer will be still between 1259-1261.

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@arjun sir , one clarification needed - 

when the page table outputs that there is a page fault , that is when the page fault service begins right ?

So , in the second part of the equation

Average memory fetch time for each instruction + Average page fault time for each instruction

= 2 * (9999/10000) * (150) [When no Page Fault occurs per instruction]

+ (1/10000) * 8 * 10^6 [ When Page Fault occurs, it is serviced which also includes the mem access time]

The first part of the equation will remain the same, is the above correct ?

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Shouldn't it be

Effective Avg. Instruction execution time

= Avg. CPU time

+ TLB hit*(TLB access time + Memory access time)x2

+ TLB Miss*(TLB access time + PageHit*[two level page accessing time + memory access time])x2

+ TLB Miss*(TLB access time + PageMiss*PageFault time)x2

=100+0.9*(0+150)*2+0.1*(0+0.9999*(3*150))*2+0.1*(0+0.0001*(8000000))*2

=619.9ns

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(1- 1/10,000 ) ->  Page fault not occured
How does this senario considered in the above equation ? Im not getting it

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Only thing I have to ask is the term "9999/10000" if we use for page hit will be placed before both page tables too as:- 

=100+2(0.9(0)+0.1( "here"*2×150))+ 2*"here"×150 + then page fault servicing..

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Had the page fault rate given per memory access, do we need to consider the possibility of page fault while accessing second level page table also?

Also, i want to clarify for multilevel paging case, do we need to have atleast 1st level page table only...I mean other levels can be paged out/in as per demand?

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We are getting 1260 ns because per access we are taking 2*150+150 (2-level page table search + memory access), whereas for 1230 ns we require only 150+150 (ONE memory access for both 2-level page table + memory access). Why will we perform only one page table search for 2-level page table is out of my reasoning.

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@Bikram sir why we are not considering memory access time in tlb hit ?

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@ set2018

Yes, in answer it is consider memory access time in case of tlb hit  ..

TLB hit should be for every memory access. So, we do (address translation time *2 ) which gives  60 ns , since each instruction has 2 memory accesses. 

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@Bikram Sir, 

For TLB we have 

TLB access time = c

Mem Access = m

TLB_hit(c+ m) + TLB_miss(c + (n+1)*m)

where n is the no of paging applied.

Now, including the concept of Page Fault Rate

Page_hit( TLB_hit(c+ m) + TLB_miss(c + (n+1)*m) ) + Page_miss( Service time)

I am not able to relate this expression to the solution provided by the Arjun Sir,

According to me, it should be:-

100 + 2*150 + 0.9999*(0.9*0 + 0.1 * (0 + (2+1)*150 )) + 0.00001*8*10^6

What is wrong in this solution???

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why (2+1)*150 ?

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I think here asked " average instruction execution time "

in that place it asked about average memory access time ans will be different

rt?

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@ Srestha (2+1) because after 2-page page table access, the translated physical address finally retrieves data from that location in memory.

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@Shubhansu

Page_hit( TLB_hit(c+ m) + TLB_miss(c + (n+1)*m) ) + Page_miss( Service time)

I think this formula is not valid here because page_hit or page_miss ratio depends on no. of instructions and not on memory accesses.

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For n level paging we use:-

 TLB_hit(c+ m) + TLB_miss(c + (n+1)*m) 

@Tuhin Dutta may you please explain me where this formula fits in Arjun sir's explanation.

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The formula can be written in this way:

TLB_hit*c + TLB_hit*m + TLB_miss*c + TLB_miss*n*m + TLB_miss*1*m

Now as per question,

n = no of page table levels; TLB access time(c) = 0; Mem Access(m) = 150 

On putting the values,

= 0.9*0 + 0.9*150 + 0.1*0 + 0.1*2*150 + 0.1*1*150 

= 0.9*0 + 0.1*2*150 + 0.9*150 + 0.1*150 

= 0.1*2*150 + 0.9*150 + 0.1*150

= 0.1*2*150 + 1*150

This bold portion should be multiplied by 2 since each instruction does 2 mem. accesses which is actually done by Arjun sir separately.

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Summary of the given solution:

Instruction: Add R1, M[1000], M[2000]

All instructions are in this format, each instruction needs 100ns CPU time, two memory access to fetch both the operands. Address translation will be done for both the operands.

Avg execution time = 100ns (cpu time) + .9*2(0)(Add translation time for both the operands TLB Hit) + .1*2*(150+150)(TLB miss for both the operands Add translation time) + 2*150(both operands are fetched from the memory) + (1/10000)*8ms ( avg page fault service time)

$= 100ns + 0 + 60ns + 300ns + 800ns = 1260ns$

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Shouldn't the last part i.e. page fault service time be multiplied by 2 as page fault can happen in both operand fetch from memory?

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@swati page fault is given per instruction but not per memory address

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@Manu

100 + 2*150 + 2*(0.9*0 + 0.1*2*150) + 800 = 1260

For TLB access, is it because we are considering two addresses so that's why 2 is multiplied?

 what, if it is an instruction with indirect addressing(operand of the instruction gives the location where the address of the actual operand is stored) then do we need to access TLB twice? 

100 + 2*150 + 0.9*0 + 0.1*2*150 + 800 = 1230

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@ arjun sir

why .0001*8ms is not multiplied by 2

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why you havent multiplied 800 by 2???

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In the question 8 ms is given but pawan sir took it as 8 micro second..

My answer is 2060 ns..

Please correct me if I am wrong

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1260 does not option even specified...

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sir i hav e a doubt.. why didn't you multiply 800 with 2? that also part of accessing the byte from memory right?

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The solution is not correct because milliseconds have been taken as microseconds.

The correct answer is 2060 nanoseconds.

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@ arjun sir,

If miss in TLB then PA should be obtained from MM from page table.

If requested Page table itself not in MM , Are we considering probability for its page fault also ??

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Will a page table access ever cause page fault? If so what happens after that?

Anyway for this question how and when page fault happens is irrelevant as page fault rate per instruction is given directly.

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Will a page table access ever cause page fault if so what happens after that?

@Arjun  Sir ...lets say in outer level page table some entry selected and for that entry referred  page table of next level is not in memory then it is loaded in memory and original access restarted again..

correct me if am wrong sir

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Never happens. A page table is always in main memory and never swapped out.

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A page table is always in main memory and never swapped out.

Means while loading new process ..ALL required page tables in all levels are loaded..so page fault happens only for pages corresponding to process and identified by valid bit in Page table..

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Yes. There is no OS mechanism to handle nested Page Faults.

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@arjun since it is 2 level paging then why you didn't multiply it with 3 because it'll take 3 memory readings??

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sir, I have a doubt.. why didn't you multiply 800 with 2?b'coz that also part of accessing the byte from memory right?

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@Ramsankar Hazra  

Go through comments. 

one more. 

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= 100+2(0.9(0)+0.1(2×150))+2×150+1/10000×8×10^6

here it should be 10^-3

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@Arjun sir, you used $\Big(0.9 (0) + 0.1 (2 \times 150)\Big)$ for 2 level paging, but why is it not $2 \times \Big(0.9 (0) + 0.1 (150)\Big)$ sir ?

By writing $\Big(0.9 (0) + 0.1 (2 \times 150)\Big)$ aren't we assuming that if we find the Page Table Entry (PTE)  of the outer page table in TLB then we will also find the PTE of the inner page table in the TLB only ?

And moreover even if we dont find the outer PTE in the TLB isn't there a chance that we might find the inner page table's PTE in the TLB ?

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https://gateoverflow.in/318/gate2004-47?show=319#a319

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I understand the solution. But i am unable to visualize the scenario plz help me to understand this.

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https://gateoverflow.in/318/gate2004-47?show=269011#a269011

 

https://gateoverflow.in/318/gate2004-47?show=97593#a97593

 

https://gateoverflow.in/318/gate2004-47?show=134354#a134354

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Here in this question  , one instruction = two memory access given .

And page fault is given per instruction .

If page fault would also be given per memory access then we have to multiply by 2.

hope u got it..

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Because the page faults are /instruction (per instruction), not /memory-ref.

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@Arjun I feel you should not multiply 2 with TLB access time because the question is specific about only 2 memory accesses for a particular instruction , so  for one instruction only 1 TLB access should be assumed ,isn't it ?

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@Arjun At least, according to several GATE questions, in case of multi-level paging, except the outer level page table, the other tables need not have all their pages in MM all the time.

That contradicts our calculations regarding multilevel paging numericals, as those questions need us to assume that the entire Page Table is in MM (just as this one does). 

However, there have been theoretical questions (such as in GATE 2003)

https://gateoverflow.in/916/gate2003-26

here it has been implied that Single level paging incurs greater memory overhead than multilevel paging. How would you explain that without assuming that in case of Multi-level paging, we can "reduce the overhead"?

So, I guess it's an ASSUMPTION we make during these numericals, thate page tables are always in MM. And it does sound more practical to me that all the levels of Page Tables should ENTIRELY be in MM. But then how would you explain the memory overhead reduction?

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@Arjun@Bikram@Ayush Upadhyaya@Kushagra गुप्ता

please tell me how are you adding the page fault service time even if it is a tlb hit..

tlb hit + page fault (or page replacement) is an impossible scenario ..

so in answer ( 8 x 10^6 / 10000 ) should be replaced by ( 8 x 10^6 / 10000 ) x 0.1

isnt it,,,? what am i missing?

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1260 option itself is not present in the question

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You can ask this to those who made options 😉

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But the correct answer is 1230 according to gate solution

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Which IIT released the GATE solution for 2004?

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it is a 2 level paging so it will need 3 memory access 1^st will give entry in 2^nd page table and second time it will give actual address so processor need to access memory 3^rd time also so so you need to multiply it by 3 instead of 2 so ultimate answer will be 1290 ns … please correct me if i am wrong.

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https://gateoverflow.in/333178/gate-2020-cse-question-53

sir if take a look on your answer for gate 2020 question then if will find that answer for this gate 2004 question is 1230.

please have a look sir

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There is a subtle wrong assumption made in this answer:​​​​​​

• T(Address translation), T(memory fetch), T(page fault service) are independent variables while they aren’t
• But T(page fault) is dependent on T(Address Translation) // if T(Address translation) is 0 (where translation is via a TLB hit), T(page fault service) is 0

While T(Instr_exec) = T(CPU_time) + T(Addr_translation) + T(mem_fetch) + T(page fault service), it is incorrect to make a similar statement on their averages as the variables aren’t independent.

 

A better split is as follows:

E(T(instr_exec)) = E(T(CPU_time)) + 2 * E(T(mem_fetch)) // mem_fetch is addr translation and mem_access
E(T(mem_fetch)) = p(tlb_hit) * T(mem_access) + (1 – p(tlb_hit)) * E(T(mem_access_on_tlb_miss))

E(T(mem_access_on_tlb_miss)) = 2 * T(mem_access) + (1 – p(page falt)) * T(mem_access) + p(page_falt_rate) * T(page_falt_service) = 1250

This makes E(T(mem_fetch)) = 0.9 * 150 + 0.1 * 1250 = 260

E(T(instr_exec)) = 100 + 2 * 260 = 620

Please correct me if I’m wrong

 

Answer 2

I think here we are overcomplicating things and question is simple but we need to understand it carefully.

 page fault rate is one in every 10,000 instructions.

 

 Page fault service time=8ms.

So, on an average time lost due to page fault per instruction=$\frac{8ms}{10000}=800ns$

Now, to this compute Memory access time using TLB.

$EMAT=0.9(150)+0.1(3*150)=180ns$

Since, 2 Memory References are made, Hence total time=$360ns$

To this, $100ns$ of cpu time.

effective average instruction execution time=$800+360+100=1260ns$

Comments

This is by far the best explanation!!

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@Jhaiyam (3*150) because once we have TLB miss, we would go to the outer page table which is located in the main memory, hence one memory access, after that, we move to the inner page table (which is also in the main memory), hence second memory access. Now we have done our V to P translation so we would access the required page from the frame number we’ve got from the inner PT, hence the third memory access.

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The most important point is, we need to consider only one page fault per instruction, rather than considering page fault for each memory access (i.e in EMAT).

Answer 3

I think this problem has two parts---

1st:- We have to calculate Instruction execution time when Instruction is in Memory.

        Execution Time in this case is---

                     TLB hit(time to execute instruction)+TLB miss(PageTable access + time to execute instruction)

                   =TLB hit(time to execute instruction)+TLB miss(2*MemoryAccessTime + time to execute instruction)

                  =TLB hit(CPU time+2*MemoryAccessTime)+TLB miss(2*MemoryAccessTime + (CPU time+2*MemoryAccessTime))

                 =0.9(400)+0.1(700)

                 =430 ns

2nd-      Now we also have to include the fact that Instruction may not be in Mainmemory.Then we have to service page fault first             then we execute instruction like above case

           So overall effective average instruction execution time would be

                      =P*(PageFaultServiceTime+InstructionExceTime when in memory)+(1-P)(InstructionExceTime when in memory)

                     =(1/10000)(8*10⁶+430)+(9999/10000)(430)=1230ns

Please let me knw if there is any issue.

Comments

yes page fault will be calculated when instruction will not be in main memory instead of tlb miss. That's why page fault will be with respect to instruction not with respect to memory access

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In the above answer,

 =TLB hit(CPU time+2*MemoryAccessTime)+TLB miss(2*MemoryAccessTime + (CPU time+2*MemoryAccessTime))

When a  mis occur then we access two page tables,after that we got physical address,now we should do one more memory reference to read that memory and then we should add + (CPU time+2*MemoryAccessTime))

Can some one clarify on this?

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@ rahul sharma 5

this answer is not correct. Chk selected ans

Answer 4

effective average instruction execution time = CPU TIME + 2 (effective memory access time )

effective memory access time= logical address To physical address + fetch the bye from memory 

                                                =  t+(1-pt)(km)+m+pf(ps) (t =tlb access time ,pt =tlb hit, k= paging level, m= memory access time ,pf page fault,ps= page service )

                                    =   0+(1-0.9)*(2*150ns)+150ns+(1/10000)(8ms)

                                     =30ns+150ns+800ns=980ns 

effective average instruction execution time= 100+2(980)=2060ns .. so ans is none of this ...

Comments

should we not get page fault only when there is TLB  miss?

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This solution is absolutely right.... and none of the options are  correct...

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memory access time should include page fault right?