A byte addressable computer has a small data cache capable of holding eight 32 bit words. Each cache block consist of two 32 bit words. For the following sequence of addresses (in hexa decimal ). Find the hit ratio if two way set associative LRU cache is used.
200, 204, 208, 20C, 2F4, 2F0, 2F4, 2F0, 21C, 218, 24C
Also find the number of... i) Misses ii) Compulsory Misses iii) Conflict iv) Capacity Misses.
--------------------------------------------------------------------------------------------------------------------------------
What bothers me is the answer given in Madeeasy Test Series. Here is my try.
A block consists of two 4B words. So, a block consists of 8B and as memory is byte addressable, 3 bits are used for offset. As well as 4 blocks are possible with above scenario and 2 sets, as a result, 1 bit is used for set.
------ | Set | Offset
200 = 0010 0000 | 0 | 000 => Compulsory Miss
204 = 0010 0000 | 0 | 100 => Hit
208 = 0010 0000 | 1 | 000 => Compulsory Miss
20C = 0010 0000 | 1 | 100 => Hit
2F4 = 0010 1111 | 0 | 100 => Compulsory Miss
2F0 = 0010 1111 | 0 | 000 => Hit
2F4 = 0010 1111 | 0 | 100 => Hit
2F0 = 0010 1111 | 0 | 000 => Hit
21C = 0010 0001 | 1 | 100 => Compulsory Miss
218 = 0010 0001 | 1 | 000 => Hit
24C = 0010 0100 | 1 | 100 => Compulsory Miss
(Other capacity and conflict misses are 0)
So, the hit ratio should be 6/11 = 0.54.
But, the answer given was 0.2
Where am I going wrong???
[P.S. - There is same qstn asked by someone previously, but I guess, that explaination is conflicting. You can check it here - https://gateoverflow.in/29182/cache-miss-in-two-way-set-associative ]