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One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called

  1. True dependency
  2. Anti-dependency
  3. Output dependency
  4. Control Hazard
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$\underline{\textbf{Answer:}\Rightarrow}\;\mathbf{c.}$

  1. $\text{WAW (Output Dependency)}$
  2. $\text{WAR (Anti-Dependency)}$
  3. $\text{RAW(Flow or True data Dependency)}$
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