The size of the physical address space of a processor is $2^{\text{P}}$ bytes. The word length is $2^{\text{W}}$ bytes. The capacity of cache memory is $2^{\text{N}}$ bytes. The size of each cache block $2^{\text{M}}$ words. For a $\text {K-Way}$ set associative cache memory, the length (in number of bits) of the tag fields is:
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$ \text {P- N- M- W +} \log \text{K}$
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$ \text {P- N- M- W } - \log_{2} \text{K}$
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$\text {P- N} + \log_{2} \text{K}$
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$\text {P- N} - \log_{2} \text{K}$
