GATE CSE 2016 Set 1 | Question: 31

Question

The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $\text{DMA}$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.

Comments

Data count register = $16$ bits.

=> Data that can be transferred at once = $2^{16}$ bytes. (Because byte addressable memory)

Total data to be transferred = $29154*1024$ bytes.

 

Number of transfers required = $29154*1024 \div 65536=455.531$

So, 456 attempts required.

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The mode(cycle stealing/burst) is not given explicitly. However, from what I have observed, devices which are relatively fast(like disk) are usually operated in burst mode while those that are relatively slow(like printer) are usually operated in cycle stealing mode.

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But still it is not compulsory.

It can work in cycle stealing mode we get ans : 0.

It can also work in transparent mode we can get ans : 1.

So all these answer should be correct right, since they haven’t written minimum or maximum?

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how much data DMA can transfer in one cycle??

I never heard of data count register. Can anybody share some reference?

Answer 1

Data count register gives the number of words the DMA can transfer in a single cycle..

Here it is $16$ bits.. so max $2^{16}$ words can be transferred in one cycle..

Since memory is byte addressable.. $1 \text{ word}=1\;\text{byte}$
                                                so $2^{16}$ bytes in $1$ cycle..
Now for the given file..
                               File size $=29154\ \textsf{KB} = 29154\times 2^{10}\ \textsf{B}$
                                                  $1$ cylce $\rightarrow$ DMA transfers $2^{16}\ \textsf{B}$
i.e 
                                             $1\ B$ transfered by DMA $\rightarrow \dfrac{1}{2^{16}}$ cycles.

Now, for full file of size $29154\ \textsf{KB},$

Minimum number of cylces $=\dfrac{(29154\times 2^{10}\ B)}{2^{16}}= 455.53$

But number of cylces is asked so $455.53\rightarrow 456.$

Comments

How to identify the DMA mode here?

Also how much data DMA can transfer in one cyle?

Please share any reference.

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In Dma mode data tranfer in form of Byte . In 1 DMA cycle 1 B is transfered.

"minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is " tells WE have to use DMA mode.

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" In 1 DMA cycle 1 B is transfered." means cycle stealing mode. But here burst mode is used.

I want to know that how to identify from this question that it is burst mode.

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In 1 cycle it is not 1 byte. It is 2^16 bytes. Hence it is DMA burst mode.

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@Ram they asked for

""MINIMUM" " number of times the DMA controller needs to get the control of the system bus from the processor...So here Burst mode is suitable.

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dont take 1KB=1000 B

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Data count register gives the number of words the DMA can transfer in a single cycle.

I think this statement requires some modification. Term "Data transfer in one go" is more appropriate than "single cycle"

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Burst mode does not mean the entire file is transferred from disk to main memory all at once. This would be impractical. What burst mode means is that, once the DMA is ready with some data from the I/O device and is granted bus request from the CPU; it will transfer the block of data which it has obtained from the I/O to MM. The size of data transferred in one go, is usually defined by the word count register.

As given in the question, the WCR = 16bits. So, in DMA burst mode we can transfer 64KB of data before DMA releases the bus. This however, still leaves the CPU inactive for that entire duration of transfer (which is quite long compared to cycle stealing).

In cycle stealing mode, one byte ( and not the entire block of data, represented by the word count register) is transferred before the DMA gives back the control of bus back to the CPU.

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In 1 cycle I think 2^16 - 1 B can be transferred.

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How is it 2^16 bytes in 1 cycle?

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By "One Cycle", it means 1 DMA Cycle. and number of bytes should be 2^16 - 1. because once the counter hits 0, DMA will relinquish the control. so we are fetching 65535 Bytes per Cycle. but taking 2^16 won't change the answer.

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@Puja Mishra

How is it 1 word = 1 byte ??

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nephron

"The memory is byte addressable" is mentioned in the question. In general we address the word and the word here is a Byte as it's byte addressable.

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@ Aakash_ Active

I dont agree - "In general we address the word".    We cannot assume 1 byte = 1 word unless mentioned

In fact why do we even need "word" for solving this question.

What is the source of Data count register gives the number of words the DMA can transfer in a single cycle... I have not seen such statement anywhere in the standard books?

@Arjun Sir please clarify this doubt

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nephron

Are you even reading the question?

It's mentioned in the question that the memory is Byte Addressable.

Data Count Register keep track of number of words to transfer. So in Burst Mode, we transfer the word till the data count register becomes 0. example: If cpu wants to transfer 100 byte(using byte addressable) and the dma is using Burst mode, DMA will transfer each byte and decrement the data count register till it becomes 0. and this complete transfer will be 1 DMA Cycle because DMA will not release the system bus to the CPU during this time.

 

and in the question actual bits are given for count register, so 2^16 - 1 bytes can be transferred before the system bus is released by the DMA

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Aakash_ Active

Now why are u assuming it is in burst mode? It is nowhere mentioned in the question. Why can't it be cycle stealing?

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nephron Everything is mentioned in the question, you need to read carefully.

 

"The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory"

In the question, minimum is asked, if we use cycle stealing, we'll be getting max value.

 

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Aakash_ Active

Isn't this conceptual error:

Since memory is byte addressable.. 1 word=1 byte

I have seen case where memory is byte addressable and 1 word = 4 bytes

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for DMA, standard textbooks talks in terms of word transfer and data count register stores the number of words to be read or written, and in this question, word size is not mentioned, so we have to assume that word size is equal to byte size. for this question 1 Word = 1 Byte.

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Aakash_ Active

As per the standard text - Stallings,  in burst mode, the DMA keeps the bus unless it has transferred. In cycle stealing, it keeps stealing 1 cycle. There is no point to assume, it is in burst or cycle-stealing mode. The ques may imply a hypothetical situation. Besides, DMA transfers in words is still acceptable. But there is no point of assuming 1 Byte = 1 word. I just wonder why do we need this 1 Byte = 1 word. We have not even used it anywhere in the question.

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Nice

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Is it appropriate to say that 1 Cycle = $2^{16}$ bytes of data transferred or it should be, 1 transfer time = $2^{16}$ bytes of data transferred? 

Correct me, if i am wrong.

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@ayushsomani

when the CPU give the control to the DMA controller then automatically 2^16 bytes will be transferred to the memory .and the number of cycles taken will depend on the memory access time.

so  I think  "1 transfer time = 216216 bytes of data transferred" this is correct.

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Here it is 16 bits.. so max 2^16 words can be transferred in one cycle..

It means we are considering unsigned number.

Why not 2's complement number?

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VERY WELL EXPLAINED @abhilashpanicker29

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Are you sure it’s 2^16 and not (2^16)-1. Anyways for this question we get the same answer for both but for some question it differs.

 I have this doubt because am told that out of 2^16 sequences, the sequence of all 0’s is used to represent that there is no data to be transferred and hence its not included.

Please correct me if am wrong.

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@arjun sir please rply to this

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@cyril you are correct. $2^{16}-1$ is the highest unsigned value the register can represent and we can transfer that much amount (bytes) of data at max in one go..

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@Deepak Poonia Sir is @cyril’s comment “ I have this doubt because am told that out of 2^16 sequences, the sequence of all 0’s is used to represent that there is no data to be transferred and hence its not included.”  True??

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@abir_banerjee doubt resolved??

Answer 2

Size of data count register of the DMA controller = 16 bits

Data that can be transferred in one go = 2¹⁶ bytes = 64 kilobytes File size to be transferred = 29154 kilobytes.

So, number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory = ceil(29154/64) = 456  

Comments

c? There are no options:p. Correct answer btw:)

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Correct answer is 456 only.

Answer 3

minimum 456

Comments

An explanation would be helpful.

Answer 4

456 cycles