Login
Register
@
Dark Mode
Profile
Edit my Profile
Messages
My favorites
Register
Activity
Q&A
Questions
Unanswered
Tags
Subjects
Users
Ask
Previous Years
Blogs
New Blog
Exams
Dark Mode
Cache Mapping
Mrityudoot
asked
in
CO and Architecture
Jun 5, 2023
edited
Jun 5, 2023
by
Mrityudoot
617
views
0
votes
0
votes
In a 2 level hierarchy, the cache has an access time of 15 ns and the main memory has an access time of 110 ns, the hit rate of the cache is 90%. If the block size of the cache is 16 Bytes, then average memory access time including miss penalty is?
co-and-architecture
cache-memory
multilevel-cache
Mrityudoot
asked
in
CO and Architecture
Jun 5, 2023
edited
Jun 5, 2023
by
Mrityudoot
by
Mrityudoot
617
views
answer
comment
Follow
share this
share
0 Comments
Please
log in
or
register
to add a comment.
Please
log in
or
register
to answer this question.
1
Answer
2
votes
2
votes
Best answer
Cache access time = 15 ns
Main memory access time = 110 ns
Block size = 16 bytes
Block access time = 16 * 110 = 1760 ns
Miss penalty means after access the memory we have to include the data in cache
Average memory access time = Hit rate of cache * cache access time + (1 – hit rate)(cache access + block access + from memory again put on cache
= 0.9 * 15 + 0.1* (15+1760+15)
= 192.5 ns
Akshat bhatt
answered
Sep 8, 2023
selected
Jan 20
by
Mrityudoot
by
Akshat bhatt
comment
Follow
share this
0 Comments
Please
log in
or
register
to add a comment.
← Previous
Next →
← Previous in category
Next in category →
Related questions
2
votes
2
votes
0
answers
1
h4kr
asked
in
CO and Architecture
Dec 27, 2022
536
views
cache miss question
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?
h4kr
asked
in
CO and Architecture
Dec 27, 2022
by
h4kr
536
views
co-and-architecture
cache-memory
multilevel-cache
0
votes
0
votes
0
answers
2
Priyansh Singh
asked
in
CO and Architecture
Jan 27, 2019
601
views
Computer organisation cache
Why can't we have n-levels of cache ?
Priyansh Singh
asked
in
CO and Architecture
Jan 27, 2019
by
Priyansh Singh
601
views
cache-memory
co-and-architecture
multilevel-cache
0
votes
0
votes
0
answers
3
Raj Singh 1
asked
in
CO and Architecture
Dec 19, 2018
1,236
views
Calculating average access time in multi level cache
$h_1→L1$ hit ratio $h_2→L2$ hit ratio $C_1→ L1$ access time $C_2→ $Miss penalty to transfer information from L2 to L1 $M→$ Miss penalty to transfer information from main memory to L2 Average access time given in Carl Hamacher's book ... red. Is my equation correct or book's equation. Or something more is going on here, which I am unaware of?
Raj Singh 1
asked
in
CO and Architecture
Dec 19, 2018
by
Raj Singh 1
1.2k
views
cache-memory
multilevel-cache
co-and-architecture
0
votes
0
votes
0
answers
4
Satbir
asked
in
CO and Architecture
Dec 6, 2018
230
views
cache
Consider a system with the average memory access time of a processor with one level (L1) cache is 2.8 clock cycles. If the required data is present in L1-cache it can be accessed in 1 clock cycle otherwise it needs 85 clock cycles to get it from memory. If another ... the access time of 6 clock cycles. What is the hit rate of L2-cache such that average memory access improved by 70%? (ans=71%)
Satbir
asked
in
CO and Architecture
Dec 6, 2018
by
Satbir
230
views
co-and-architecture
cache-memory
multilevel-cache
average-memory-access-time
numerical-answers
Subscribe to GATE CSE 2024 Test Series
Subscribe to GO Classes for GATE CSE 2024
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Post GATE 2024 Guidance [Counseling tips and resources]
GATE CSE 2024 Result Responses
[Project Contest] Pytorch backend support for MLCommons Cpp Inference implementation
Participating in MLCommons Inference v4.0 submission (deadline is February 23 12pm IST)
IIITH PGEE 2024 Test Series by GO Classes
Subjects
All categories
General Aptitude
(3.5k)
Engineering Mathematics
(10.4k)
Digital Logic
(3.6k)
Programming and DS
(6.2k)
Algorithms
(4.8k)
Theory of Computation
(6.9k)
Compiler Design
(2.5k)
Operating System
(5.2k)
Databases
(4.8k)
CO and Architecture
(4.0k)
Computer Networks
(4.9k)
Artificial Intelligence
(79)
Machine Learning
(48)
Data Mining and Warehousing
(25)
Non GATE
(1.4k)
Others
(2.7k)
Admissions
(684)
Exam Queries
(1.6k)
Tier 1 Placement Questions
(17)
Job Queries
(80)
Projects
(11)
Unknown Category
(870)
64.3k
questions
77.9k
answers
244k
comments
80.0k
users
Recent Blog Comments
category ?
Hi @Arjun sir, I have obtained a score of 591 in ...
download here
Can you please tell about IIT-H mtech CSE self...
Please add your admission queries here:...
Twitter
WhatsApp
Facebook
Reddit
LinkedIn
Email
Link Copied!
Copy