Hit Latency | Computer Organization

Ray Tomlinson asked in CO and Architecture Aug 22, 2023

230 views

0 votes

is this formula is correct if it is correct then in gate 2006 Question 75 why they not used this formula

https://gateoverflow.in/43565/gate-cse-2006-question-75

co-and-architecture
cache-memory
computer-architecture

Ray Tomlinson asked in CO and Architecture Aug 22, 2023

by Ray Tomlinson

230 views

0 Comments

Please log in or register to add a comment.

Please log in or register to answer this question.

0 Answers

← Previous Next →

← Previous in category Next in category →

Related questions

0 votes

1 answer

Ray Tomlinson asked in CO and Architecture Aug 19, 2023

444 views

Computer Organisation Textbook Questions
Consider the case memory which has 0.8 and 0.9 hit ratio for read and write operation. Whenever there exist here miss either read or write 2 word block is to be moved from main memory to case memory. The case access time is ... time for read operation, 2. second find average access time for write operation, 3. average access time overall and throughput.

Ray Tomlinson asked in CO and Architecture Aug 19, 2023

by Ray Tomlinson

444 views

co-and-architecture
reference-book
computer-architecture
cache-memory
carl-hamacher

1 vote

0 answers

AnilGoudar asked in CO and Architecture Nov 9, 2017

932 views

Hit latency in Cache
How to approach hit latency problems in cache mapping techniques. Please explain with an example. Thank in advance.

AnilGoudar asked in CO and Architecture Nov 9, 2017

by AnilGoudar

932 views

co-and-architecture
cache-memory
hit-latency

22 votes

3 answers

pC asked in CO and Architecture Jul 27, 2016

6,773 views

Self Made: Hit Latency
Cache 1 Direct Mapping 17 tag 10 block 5 word Cache 2 Set Assosicative 2- way associative 18 9 5 Cache 3 Associative Cache 27 5 Calculate Hit Latenncy in Each of Three Cache Memory if 2 to 1 MUX / OR has latency of 0.6ns k-bit comparator has katency of k/10 ns 2.How much number of MUX / OR ? camparators are used in each of three

pC asked in CO and Architecture Jul 27, 2016

by pC

6.8k views

co-and-architecture
cache-memory
hit-latency
self-made

0 votes

2 answers

Chandra Kishore asked in CO and Architecture Jun 5, 2016

2,302 views

Cache has a hit rate of 95%, 128 byte lines and a cache hit latency of 5 ns
A cache has a hit rate of 95 percent, 128-byte lines, and a cache hit latency of 5 ns. The main memory takes 100 ns to return the first word(32 bits) of a line, and 10 ns to return each subsequent word. What ... assume that the cache takes the same amount of time to detect that a miss has occurred as to handle a cache hit.)

Chandra Kishore asked in CO and Architecture Jun 5, 2016

by Chandra Kishore

2.3k views

co-and-architecture
cache-memory

Subscribe to GATE CSE 2024 Test Series

Subscribe to GO Classes for GATE CSE 2024

Quick search syntax

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

Subjects

All categories
General Aptitude (3.5k)
Engineering Mathematics (10.4k)
Digital Logic (3.6k)
Programming and DS (6.2k)
Algorithms (4.8k)
Theory of Computation (6.9k)
Compiler Design (2.5k)
Operating System (5.2k)
Databases (4.8k)
CO and Architecture (4.0k)
Computer Networks (4.9k)
Artificial Intelligence (79)
Machine Learning (48)
Data Mining and Warehousing (25)
Non GATE (1.4k)
Others (2.7k)
Admissions (684)
Exam Queries (1.6k)
Tier 1 Placement Questions (17)
Job Queries (80)
Projects (11)
Unknown Category (870)

64.3k questions

77.9k answers

244k comments

80.0k users

Recent Blog Comments

category ?
Hi @Arjun sir, I have obtained a score of 591 in ...
download here
Can you please tell about IIT-H mtech CSE self...
Please add your admission queries here:...

Send feedback
Rank Predictor
College Prediction
Useful Links
FAQ
Corrections
Discuss
Copyright
Request
Testimonials
Chat Logs
Chat
Badges
Search tips
Exam Category
Blog Category
Blog Tags
Privacy
Test Series
GATER
Refund Policy
Terms and Conditions
Contact Us

Developed by Chun

Hit Latency | Computer Organization

0 Comments

Please log in or register to add a comment.

Please log in or register to answer this question.

0 Answers

Related questions

Subscribe to GATE CSE 2024 Test Series

Subscribe to GO Classes for GATE CSE 2024

Recent Posts

Subjects

Recent Blog Comments