Which kind of data dependence can cause data hazards in a single-core, pipelined, in-order processor? (Mark all that apply.)
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Detailed Video Solution: https://youtu.be/dTMRxm43nd0?feature=shared&t=732 Proof that WAW $\&$ WAR hazards are NEVER possible in an in-order pipeline: https://youtu.be/uJkGMjP6hzE?feature=shared&t=4302 WAW (write after write), and WAR (write after read) hazards are not an issue in our pipeline (in-order pipeline) because we never change the order of instructions while executing them. A preceding instruction is always ahead of a succeeding instruction in the pipeline. This is an example of an in-order pipeline. In-order pipeline simply executes instructions in the sequence they appear in the program $\&$ If instruction $\text{I}$ comes before instruction $\text{J}$ in the program then during execution in the pipeline, $\text{I}$ always stays ahead of the instruction $\text{J}.$ In comparison, modern processors have out-of-order pipelines that may execute instructions in different orders than they appear in the program. In an in-order pipeline (such as our MIPS $5$-stage pipeline), a preceding instruction is always ahead of a succeeding instruction in the pipeline.
Modern processors use out-of-order pipelines that break this rule and it is possible for later instructions to execute before earlier instructions. WAW and WAR hazards are relevant only for modern out-of-order processors. Pipeline Complete Course Playlist: https://youtube.com/playlist?list=PLIPZ2_p3RNHhs9DfAY9ry6XbjGn7ZumZ8&feature=shared
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