A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of instructions corresponding to the statement X = (S - R * (P + Q))/T is given below. The values of variables P, Q, R, S and T are available in the registers R0, R1, R2, R3 and R4 respectively, before the execution of the instruction sequence.
ADD |
R5, R0, R1 |
; R5 ← R0 + R1 |
MUL |
R6, R2, R5 |
; R6 ← R2 * R5 |
SUB |
R5, R3, R6 |
; R5 ← R3 - R6 |
DIV |
R6, R5, R4 |
; R6 ← R5/R4 |
STORE |
R6, X |
; X ← R6 |
are
I4 - I5 (R6) and I3-I4(R6) anti data dependency ?