throughput-CO-vgate

Question

please explain ur answer

Answer 1

Average CPI =0.4(4) + 0.2(5) + 0.4(6) =5cycles

1 cycle= 10ns

Total time taken by single instruction = 5 cycles + 2ns(Overhead)   =52ns

So, in one Second= 1000/52 MIPS = 19 (integer value only)

Answer 2

As they are asking for pipeline system for pipeline per instruction takes one clock cycle they hv not mentioned anythying speific so we ll neglect stall cycles

here 1 clock cycles takes 12 ns for pipeline so in 1 sec 200 MIPS

Answer 3

For pipelined system it should be 1/12ns which means 83MIPS.,10ns is the clock cycle 2ns is overhead so total 12ns