GATE CSE 2015 Set 1 | Question: 8

Question

For computer based on three-address instruction formats, each address field can be used to specify which of the following:

(S1) A memory operand

(S2) A processor register

(S3) An implied accumulator register

• A. Either $S1$ or $S2$
• B. Either $S2$ or $S3$
• C. Only $S2$ and $S3$
• D. All of $S1$, $S2$ and $S3$

Comments

implied addressing modes have one of the operand (destination i.e the accumalator ) as fixed hence we always use only one address in the instruction which may be a memory address or a register like LOAD X   or  LOAD R1  this will load the contents of the memory locations or the registers to the implied operand which is the accumulator we need not specify the accumulator explicitly in the instruction

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Implied Accumulator is used in Single Accumulator Organization:

https://conceptsofcomputer.wordpress.com/tag/implied/

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For those asking "what if 3-address code instead", from Wikipedia -:

"Since three-address code is used as an intermediate language within compilers, the operands will most likely not be concrete memory addresses or processor registers, but rather symbolic addresses that will be translated into actual addresses during register allocation."

Answer 1

Three address Instruction

Computer with three addresses instruction format can use each address field to specify either processor register or memory operand.

e.g., $X = (A + B) * (C + A)$

Equivalent Three address Instructions$$\begin{array}{ll}
\text{ADD } R1, A, B &    ;\qquad R1 \leftarrow  M [A] + M [B]\\
\text{ADD }R2, C, D & ;\qquad R2 \leftarrow  M [C] + M [D]\\
\text{MUL } X, R1, R2    & ;\qquad M [X] \leftarrow  R1 * R2
\end{array}$$The advantage of the three address formats is that it results in short program when evaluating arithmetic expression. The disadvantage is that the binary-coded instructions require too many bits to specify three addresses.

Correct Answer: $A$

Comments

According to Carl Hamacher, it is given that, Instructions in modern CISC processors typically do not use a three-address format. Most ALU instructions use the two-address format.

That means RISC only use 3-address format and for RISC, the operations can only be performed in registers and not directly from the memory. Then how S1 can be true? Please explain.

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@Aarvi Chawla read Arjun sir's comment in the comment section of question 
it will be clear

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I think

R2 should be M[C]+M[A]

Answer 2

option A either A memory operand or  A processor register.

Comments

no it should be option c

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in place of 3 address instruction if it is 3 address code then ans will D??

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@rajan

Then all S1,S2,S3 should be ans.

Like ADD X

ACC ← ACC + X

Answer 3

Option A: (in inst' n never present accumulator register address)

Answer 4

Ans : A

Classification of Instructions Based on CPU Organisations

Computers may have instructions of several different lengths containing varying number of  addresses. The number of address fields in the instruction format of a computer depends on the internal organization of its registers. Most computers fall into one of the three types of CPU organizations:

(i) Single Accumulator Organization: In this type of organization all operations are performed on an implied accumulator. The instruction format uses only one address field. For example, the instruction that loads the accumulator with the contents of a memory location.

LoadX

Where X is the address of the source operand. This results in the operation AC ÷— M (X). AC is the accumulator and M(X) symbolizes the memory word located at address X.

(ii) General Register Organisation : In this organization, the instruction format needs 2 or 3 register address fields according to the operation.

For example, an instruction for addition may be written as

ADD R1, R2, R3,

It denotes the operation R1 <—R2 -f- R3

The same ADD instruction needs only two register address fields if the destination register is one of the source registers, i.e. if the operation is

R1 R1 + R2

Then the instruction is ADD R1, R2

The instruction may also contain one memory address field and one register address field. For example, the instruction,

ADD R1, X

Specifies the operation R1 —R1 + M [X]

(iii) Stack Organization : In this organization, the computers will have PUSH and POP instructions which require an address field. For Kathplê, the instruction PUSH X will push the word at address Xonto the top of the stack. The operation — type instructions do not need any address field. For example, the instruction

ADD

Consists of only opcode and no address field. It has the effect of popping the top two numbers from the stack, adding them, and pushing the sum onto the stack. Thus all the operands are implied to be in the stack.

Most of the computers fall into one of the above three types of organizations. Some computers combine features from more than one organizational structure.