GATE CSE 2002 | Question: 1.21

Question

In $2's$ complement addition, overflow

• A. is flagged whenever there is carry from sign bit addition
• B. cannot occur when a positive value is added to a negative value
• C. is flagged when the carries from sign bit and previous bit match
• D. None of the above

Comments

Overflow condition can be written in any of the three ways – 

1. $C_{n} \oplus C_{n-1}=1$ which says that either 1st MSB or 2nd MSB should give carry but not both.
2. $A_{n}B_{n}\bar{C_{n-1}} + \bar{A_{n}}\bar{B_{n}}C_{n-1}=1$ where $A_n$ and $B_n$ are the MSB (which are sign bits) and $C_{n-1}$ is the carry from the 2nd MSB.
3. $A_{n}B_{n}\bar{R_{n}} + \bar{A_{n}}\bar{B_{n}}R_{n}=1$ where $R_{n}$ is the MSB (sign bit) of result of the addition.

From the third condition above, we can see that overflow will happen when:

 1. $A_n,B_n$ is 0 (which means positive numbers) and $R_n$ is 1 (which means a negative number).

2. $A_n,B_n$ is 1 (which means both are negative numbers) and $R_n$ 0 (which means a positive number).

Conclusion: For overflow to happen, two positive numbers are added and the result is negative OR two negative numbers are added and the result is positive.

PS: 2nd result can be derived from 1st result by replacing the value of $C_n$ with $A_nB_n + C_{n-1}(A_n \oplus B_n)$ and 3rd result can be derived from the 2nd result by thinking a bit. Let me know if you find it difficult to derive it.

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1. In 2′s complement addition,carry always doesn’t indicate overflow.

2. When we will add a positive value (+a) with a negative value(-b). The result will be in between them means -b<= result <= +a. So overflow can not occur. As if we can represent -b and +a in some fixed number of bits then we can also represent any number between them.

3. In 2′s complement addition, overflow is flagged when the carries from sign bit and previous bit did not match. i.e Cn⊕Cn−1=1.

Answer 1

(B) is the answer. When a positive value and negative value are added overflow never happens. 

http://sandbox.mc.edu/~bennet/cs110/tc/orules.html

Comments

Sir , in case of unsigned numbers .. 2's complement addition of a positive and negative number can yield an overflow .

Here nothing is given about signed or unsgned numbers .. so what will be the answer ?

None of the above?

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In Morris mano, it is given that in case of signed numbers overflow can occur when the carry from priveous bits and current bits are different...

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positive value is added with negative value, i.e it's a 2's complement substraction & In 2's complement substraction, carry can come out, but this carry doesn't indicate overflow, as it's on 2's complement.

This is the flow of logic here ???

Answer 2

 

   1 0 1 0     = -6

   0 1 1 0     = +6

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1 0 0 0 0     =  0     

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Here we add +ve and -ve no. which generate carry but it is not overflow i.e we can ignore it.

Answer 3

• A. In 2′s complement addition,carry always doesn’t indicate overflow.

• B. When we will add a positive value (+a) with a negative value(-b). The result will be in between them means -b<= result <= +a. So overflow can not occur. As if we can represent -b and +a in some fixed number of bits then we can also represent any number between them.

      C. In 2′s complement addition, overflow is flagged when the carries from sign bit and previous bit did not match.                 i.e Cn⊕Cn−1=1.

      Answer: B

Comments

 “ C. In 2′s complement addition, overflow is flagged when the carries from sign bit and previous bit did not match. “  
What do you mean by overflow is flagged??

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means overflow detected.