Cache and arrays

Question

Consider below code written in C  
         Loop A
sum = 0;
 for (i = 0; i < 128; i++)
for (j = 0; j < 64; j++)
        sum += A[i][j];
         Loop B
sum = 0;
for (j = 0; j < 64; j++)
for (i = 0; i < 128; i++)
                                    sum += A[i][j];
The matrix A is stored contiguously in memory in row-major order. Consider a 4KB direct-mapped data cache with 8-word (32-byte) cache lines.

The L2 cache in the Pentium 4 holds 256 KBytes of data. The cache is 8-way set associative. Each block holds 128 bytes of data. If physical addresses is 32 bits long, each data word is 32 bits, and entries are word addressable, what bits of the 32 bit physical address comprise the tag, index and offset?

i)(19,8,8)

ii)(20,8,7)

iii)(17,8,7)

iv)(18,8,6)

Answer 1

third one is correct???

Comments

Yup solution is 17 8 7 for tag set and offset Field