GATE CSE 2002 | Question: 8

Question

Consider the following circuit. $A = a_2a_1a_0$ and $B=b_2b_1b_0$ are three bit binary numbers input to the circuit. The output is $Z=z_3z_2z_1z_0$. R0, R1 and R2 are registers with loading clock shown. The registers are loaded with their input data with the falling edge of a clock pulse (signal CLOCK shown) and appears as shown. The bits of input number A, B and the full adders are as shown in the circuit. Assume Clock period is greater than the settling time of all circuits.

a. For 8 clock pulses on the CLOCK terminal and the inputs $A, B$ as shown, obtain the output $Z$ (sequence of $4-bit$ values of $Z).$ Assume initial contents of $R_0, R_1$ and $R_2$ as all zeros. $$\begin{array}{|l|l|l|l|l|l|l|l|l|} \hline \text{A} & 110 & 011 & 111 & 101 & 000 & 000 & 000 & 000\\\hline \text{B} & 101 & 101 & 011 & 110 & 000 & 000 & 000 & 000 \\\hline  \text{Clock No} & 1 & 2 & 3 &4 &5 &6 &7&8\\\hline \end{array}$$
b. What does the circuit implement?

Answer 1

(A)$$\begin{array}{|l|l|}\hline & \textbf{output Z}\\\hline \text{Clock-1}& 0000 \\\hline \text{Clock-2}& 0000 \\\hline \text{Clock-3}& 1011 \\\hline \text{Clock-4}& 1000 \\\hline \text{Clock-5}& 1010 \\\hline \text{Clock-6}& 1011 \\\hline \text{Clock-7}& 0000 \\\hline \text{Clock-8}& 0000 \\\hline \end{array}$$
(B) The circuit is a $3-bit$ ripple binary adder.

Comments

Considering EA to be full adders. I think last 4 clock pulses Z should be 0. 

Clock	Z
1	1011
2	1000
3	1010
4	1011
5	0000
6	0000
7	0000
8	0000

Clock is applied simultaneously to  all registers and also it is assumed clock period is greater than the settling time of all circuits.

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The values are loaded into the registers at falling edge, so the calculation is done based on previous values, and then the new values are updated, which are used in next clock pulse.

So basically the values in z3z2z1z0 will be delayed by 2 clock pulses (reason already explained in above comments) and hence we have 0000 for first two rows and from 3rd row onwards we have the correct sum corresponding to A0B0, A1B1 and so on.

Reason for delay:- 

initially all three registers have values as 0

At 1^st clock, at falling edge of 1^st clock pulse, R0 will be updated with the values of A0 (i.e. a2a1a0) and B0(i.e. b2b1b0), R1 and R2 will still have 0s. So, R2 will produce output as 0000 because it is taking values from R1 which is still having 0s.

At 2^nd clock, at falling edge, R1 will be updated with the values of R0 so R1 will now have results corresponding to A0B0. R0 will receive the next set of inputs i.e. A1B1. R2 will still receive the previous value of R1 and will produce 0000

At 3^rd clock, at falling edge, again R0, R1 will be updated accordingly as explained above. But now R2 will also receive the values corresponding to A0B0 and will produce the output for A0B0 – 1011

Like this, it will continue.

If you try to analyse the exact values of each register in each clock and then produce the output, then it will be very confusing because they will contain different values corresponding to different inputs – it will be hard to keep track of them. However, once you understand the working and come to the conclusion that output produced is delayed by 2 clock pulses then it can be solved easily

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What’s happening here is ,

the result is out only after the 3^rd clock pulse, so the first two clock pulses output 0000 , and after the third clock pulse every output is directly dependent on the input , because the output is propagated downwards. 

is this correct reasoning?

@Abhrajyoti00