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Registers R1 and R2 contain memory address and data to be written in that memory adress respectively. To execute the instruction that transfers content of R2 to memory adress pointed by R1 we would first need to transfer content of R1 to MAR and R2 to MDR.
MAR <- R1
MDR <- R2
Can both of these operations be performed in same clock cycle?
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No it will require 2 cycles. Bacause we have a common bus. At one time we can't activate the load signal bith the register in one clock. otherwise they will be loaded with same value. And even bus can contain 1 thing at a time. so 2 cycles will be needed

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