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Recent questions tagged assembly
0
votes
4
answers
1
UGC NET CSE | December 2018 | Part 2 | Question: 15
Consider the following $\textsf{x}86$ - assembly language instructions: MOV AL, 153 NEG AL The contents of the destination register $AL$ (in $8$-bit binary notation), th status of Carry Flag $(CF)$ and Sign Flag $(SF)$ ... $AL=0110 \: 0110; \: CF=1; \: SF=1$ $AL=0110 \: 0111; \: CF=1; \: SF=0$
Arjun
asked
in
CO and Architecture
Jan 2, 2019
by
Arjun
3.8k
views
ugcnetcse-dec2018-paper2
co-and-architecture
assembly
non-gate
0
votes
4
answers
2
UGC NET CSE | July 2018 | Part 2 | Question: 97
Match the items in $\textbf{List-I}$ and $\textbf{List-II}$ ... $\text{(a)-(iii), (b)-(i), (c)-(ii)}$ $\text{(a)-(iii), (b)-(iv), (c)-(ii)}$
Pooja Khatri
asked
in
CO and Architecture
Jul 13, 2018
by
Pooja Khatri
2.6k
views
ugcnetcse-july2018-paper2
co-and-architecture
assembly
interrupts
0
votes
1
answer
3
UGC NET CSE | December 2008 | Part 2 | Question: 37
An assembly program contains : imperative and declarative statements imperative and assembler directives imperative and declarative statements as well as assembler directives declarative statements and assembler directives
rishu_darkshadow
asked
in
CO and Architecture
Sep 26, 2017
by
rishu_darkshadow
7.0k
views
ugcnetcse-dec2008-paper2
co-and-architecture
assembly
1
vote
0
answers
4
GATE CSE 1989 | Question: 6b
In a certain computer system, there is special instruction implemented to call subroutines. The instruction is JSR Reg.Sub Microsequence: Temp ← Sub SP ← (SP)+2 (SP) ← (Reg) Reg ← (PC) PC ← (Temp) Where Temp is an internal CPU ... would implement co-routine using the JSR instruction. Show the control flow diagram and the contents of the stack before and after the call.
makhdoom ghaya
asked
in
CO and Architecture
Dec 1, 2016
by
makhdoom ghaya
457
views
gate1989
descriptive
co-and-architecture
assembly
unsolved
1
vote
1
answer
5
UGC NET CSE | August 2016 | Part 2 | Question: 32
The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B $00H$ $35H$ $EFH$ $2FH$
makhdoom ghaya
asked
in
CO and Architecture
Sep 26, 2016
by
makhdoom ghaya
6.1k
views
ugcnetcse-aug2016-paper2
co-and-architecture
assembly
8085-microprocessor
1
vote
1
answer
6
UGC NET CSE | December 2010 | Part 2 | Question: 35
Macro-processors are ______. Hardware Compiler Registers None of the above
makhdoom ghaya
asked
in
CO and Architecture
Sep 8, 2016
by
makhdoom ghaya
2.6k
views
ugcnetcse-dec2010-paper2
co-and-architecture
assembly
8085-microprocessor
1
vote
1
answer
7
UGC NET CSE | December 2010 | Part 2 | Question: 32
'Macro' in an assembly level program is _______. Sub program A complete program A hardware portion Relative coding
makhdoom ghaya
asked
in
CO and Architecture
Sep 8, 2016
by
makhdoom ghaya
2.2k
views
ugcnetcse-dec2010-paper2
co-and-architecture
assembly
macros
0
votes
2
answers
8
UGC NET CSE | December 2010 | Part 2 | Question: 31
Object code is the output of ______. Operating System Compiler or Assembler Only Assembler Only Compiler
makhdoom ghaya
asked
in
CO and Architecture
Sep 8, 2016
by
makhdoom ghaya
1.3k
views
ugcnetcse-dec2010-paper2
co-and-architecture
assembly
0
votes
1
answer
9
UGC NET CSE | June 2011 | Part 2 | Question: 34
In which way(s) a macroprocessor for assembly language can be implemented? Independent two-pass processor Independent one-pass processor Expand macrocalls and substitute arguments All of the above
makhdoom ghaya
asked
in
Others
Aug 30, 2016
by
makhdoom ghaya
996
views
ugcnetcse-june2011-paper2
co-and-architecture
microprocessors
assembly
3
votes
4
answers
10
UGC NET CSE | December 2015 | Part 3 | Question: 2
What will be the output at $\text{PORT1 }$if the following program is executed? MVI B, 82H MOV A, B MOV C, A MVI D, 37H OUT PORT1 HLT $37H$ $82H$ $B9H$ $00H$
go_editor
asked
in
CO and Architecture
Aug 9, 2016
by
go_editor
8.7k
views
ugcnetcse-dec2015-paper3
8086
assembly
co-and-architecture
non-gate
2
votes
1
answer
11
UGC NET CSE | Junet 2015 | Part 3 | Question: 3
The RST 7 instruction in 8085 microprocessor is equal to CALL 0010 H CALL 0034 H CALL 0038 H CALL 003C H
go_editor
asked
in
CO and Architecture
Jul 31, 2016
by
go_editor
3.7k
views
ugcnetcse-june2015-paper3
8085-microprocessor
assembly
language
non-gate
co-and-architecture
1
vote
1
answer
12
UGC NET CSE | Junet 2015 | Part 2 | Question: 31
Match the following: ... $a-iii, b-iv, c-ii, d-i$ $a-iv, b-i, c-iii, d-ii$ $a-iv, b-iii, c-ii, d-ii$
go_editor
asked
in
CO and Architecture
Jul 30, 2016
by
go_editor
1.7k
views
ugcnetcse-june2015-paper2
assembly
0
votes
1
answer
13
UGC NET CSE | September 2013 | Part 3 | Question: 33
The instruction : MOV CL, [BX] [DI] + 8 represents the ____ addressing mode Based Relative Based Indexed Indexed Relative Register Indexed
go_editor
asked
in
CO and Architecture
Jul 24, 2016
by
go_editor
2.4k
views
ugcnetcse-sep2013-paper3
co-and-architecture
assembly
addressing-modes
2
votes
3
answers
14
UGC NET CSE | June 2013 | Part 3 | Question: 44
Interrupt which arises from illegal or erroneous use of an instruction or data is Software interrupt Internal interrupt External interrupt None of the above
go_editor
asked
in
CO and Architecture
Jul 17, 2016
by
go_editor
3.0k
views
ugcnetcse-june2013-paper3
co-and-architecture
assembly
interrupts
2
votes
1
answer
15
UGC NET CSE | June 2013 | Part 3 | Question: 43
What is not a p typical program control instruction? MR JMP SHL TST
go_editor
asked
in
CO and Architecture
Jul 17, 2016
by
go_editor
2.3k
views
ugcnetcse-june2013-paper3
co-and-architecture
assembly
2
votes
2
answers
16
UGC NET CSE | June 2013 | Part 3 | Question: 42
Computers can have instruction formats with only two address and three address instructions only one address and two address instructions only one address, two address and three address instructions zero address, one address, two address and three address instructions
go_editor
asked
in
CO and Architecture
Jul 17, 2016
by
go_editor
1.8k
views
ugcnetcse-june2013-paper3
co-and-architecture
assembly
instruction-format
4
votes
1
answer
17
UGC NET CSE | June 2013 | Part 3 | Question: 41
Which of the following is not an addressing mode? Register indirect Autoincrement Relative indexed Immediate operand
go_editor
asked
in
CO and Architecture
Jul 17, 2016
by
go_editor
2.7k
views
ugcnetcse-june2013-paper3
co-and-architecture
assembly
addressing-modes
0
votes
2
answers
18
UGC NET CSE | June 2016 | Part 3 | Question: 4
The Register that stores all interrupt requests is Interrupt mask register Interrupt service register Interrupt request register Status register
Sanjay Sharma
asked
in
CO and Architecture
Jul 11, 2016
by
Sanjay Sharma
3.2k
views
ugcnetcse-june2016-paper3
co-and-architecture
assembly
0
votes
1
answer
19
assembly code
Sourabh Kumar
asked
in
CO and Architecture
Jun 10, 2016
by
Sourabh Kumar
733
views
assembly
0
votes
0
answers
20
ASSEMBLY
Sanjay Sharma
asked
in
Programming in C
May 11, 2016
by
Sanjay Sharma
378
views
assembly
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