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Recent questions tagged instruction-format
6
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4
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61
ISRO2016-24
In which class of Flynn's taxanomy, Von Neumann architecture belongs to? SISD SIMD MIMD MISD
sourav.
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in
CO and Architecture
Jul 3, 2016
by
sourav.
9.7k
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co-and-architecture
isro2016
instruction-format
67
votes
4
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62
GATE CSE 2016 Set 2 | Question: 31
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and twelve-bit immediate value. Each ... program has $100$ instructions, the amount of memory (in bytes) consumed by the program text is _________.
Akash Kanase
asked
in
CO and Architecture
Feb 12, 2016
by
Akash Kanase
20.9k
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gatecse-2016-set2
instruction-format
machine-instruction
co-and-architecture
normal
numerical-answers
3
votes
2
answers
63
MadeEasy Test Series: CO & Architecture - Instruction Format
The format of a double operand instruction of a CPU consist of 4 bit op-code and 4 bits for source and destination. 12 double operand instructions and 24 single operand instructions must be implemented. Op-code ... three groups of n-operand instructions. Calculate the total number of zero operand instructions that can be implemented?
khushtak
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in
CO and Architecture
Jan 21, 2016
by
khushtak
2.0k
views
made-easy-test-series
co-and-architecture
instruction-format
2
votes
1
answer
64
MadeEasy Test Series: CO & Architecture - Instruction Format
worst_engineer
asked
in
CO and Architecture
Dec 24, 2015
by
worst_engineer
2.5k
views
co-and-architecture
instruction-format
made-easy-test-series
6
votes
4
answers
65
ISRO2009-79
Compared to CISC processors,RISC processors contain More register and smaller instruction set larger instruction set less registers and smaller instruction set more transistor elements
ajit
asked
in
CO and Architecture
Oct 5, 2015
by
ajit
3.9k
views
isro2009
co-and-architecture
instruction-format
12
votes
3
answers
66
Max number of one address instruction, when two address instruction is given is?
A computer uses expanding opcode. It has 16 bit instructions 6 bit addresses, it supports one address, two address instructions only. If there are n two address instructions, the maximum number of one address instructions are?
Tehreem
asked
in
CO and Architecture
Sep 9, 2015
by
Tehreem
11.7k
views
co-and-architecture
addressing-modes
machine-instruction
instruction-format
22
votes
2
answers
67
GATE CSE 1994 | Question: 3.2
State True or False with one line explanation Expanding opcode instruction formats are commonly employed in RISC. (Reduced Instruction Set Computers) machines.
Kathleen
asked
in
CO and Architecture
Oct 4, 2014
by
Kathleen
4.7k
views
gate1994
co-and-architecture
machine-instruction
instruction-format
normal
true-false
49
votes
6
answers
68
GATE CSE 2014 Set 1 | Question: 9
A machine has a $32\text{-bit}$ architecture, with $1\text{-word}$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ instructions, which have an immediate operand in ... to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________
go_editor
asked
in
CO and Architecture
Sep 26, 2014
by
go_editor
18.3k
views
gatecse-2014-set1
co-and-architecture
machine-instruction
instruction-format
numerical-answers
normal
42
votes
4
answers
69
GATE CSE 1992 | Question: 01-vi
In an $11$-bit computer instruction format, the size of address field is $4$-bits. The computer uses expanding OP code technique and has $5$ two-address instructions and $32$ one-address instructions. The number of zero-address instructions it can support is ________
Kathleen
asked
in
CO and Architecture
Sep 12, 2014
by
Kathleen
13.1k
views
gate1992
co-and-architecture
machine-instruction
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normal
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