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Recent questions tagged instruction-format
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31
Testbook Test Series: CO & Architecture - Instruction Format
A processor has $128$ distinct instructions. A $24-$bit instruction word has an opcode, register, and operand.The number of bits available for the operand field is $7.$The maximum possible value of the general-purpose register is _________
Lakshman Bhaiya
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in
CO and Architecture
Dec 23, 2018
by
Lakshman Bhaiya
1.1k
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testbook-test-series
co-and-architecture
instruction-format
0
votes
2
answers
32
AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.
shaz
asked
in
CO and Architecture
Dec 13, 2018
by
shaz
707
views
instruction-format
machine-instruction
2
votes
0
answers
33
MadeEasy Test Series: CO & Architecture - Instruction Format
How they have calculated the memory address part?
Gupta731
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in
CO and Architecture
Nov 15, 2018
by
Gupta731
1.1k
views
made-easy-test-series
co-and-architecture
instruction-format
1
vote
2
answers
34
MadeEasy Test Series: CO & Architecture - Instruction Format
How will this question be solved?
nephron
asked
in
CO and Architecture
Oct 24, 2018
by
nephron
955
views
co-and-architecture
instruction-format
made-easy-test-series
numerical-answers
0
votes
2
answers
35
Number of bits - Instruction format
A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 ... and an address part. How many bits are there in the operation code, the register code part, and the address part respectively?
Balaji Jegan
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in
CO and Architecture
Oct 16, 2018
by
Balaji Jegan
7.4k
views
co-and-architecture
instruction-format
numerical-answers
1
vote
1
answer
36
Computer Organization
Consider the following program segment used to execute on a hypothetical processor. Consider all the registers are of 16 bit size I1 MOV CX,0005 ; CX ← 0005 I2 MOV BX,OFF7H ; BX ← OFF7H I3 MOV AX,OBCAH ; AX ← OBCAH I4 OR BX,AX ; BX ← ... 4 cycles and transfer of control operations takes 2 cycles to execute. How much time is required to execute the program on a above CPU?
Sumit Singh Chauhan
asked
in
CO and Architecture
Sep 2, 2018
by
Sumit Singh Chauhan
2.2k
views
computer-architecture
machine-instruction
instruction-format
4
votes
1
answer
37
Computer Organization
A computer has 256 K word memory. The instruction format has 4 fields i.e., Opcode, register field to represent one of the 60 processor registers, mode field represent one of 7 addressing modes and memory address field. How many instructions the system supports when a 32- bit instruction is placed in the one memory cell.
Sumit Singh Chauhan
asked
in
CO and Architecture
Sep 2, 2018
by
Sumit Singh Chauhan
13.0k
views
computer-architecture
machine-instruction
instruction-format
2
votes
3
answers
38
Instruction Format
Consider a computer has 64 registers and support 15 different instructions. Each instruction has 4 fields i.e. opcode, source register, destination register and immediate value of 6 bits. If each instruction in byte aligned and 50 instructions are ... answer My question is, in this question what is difference between computer has 15 instruction and memory has 50 instructions?
srestha
asked
in
CO and Architecture
Jun 7, 2018
by
srestha
2.5k
views
machine-instruction
instruction-format
co-and-architecture
1
vote
2
answers
39
Ace Test Series 2019: Number Of Zero Address Instructions
A system has 16 bits instruction that support zero address, one address and two address instructions Assume each address field size is 5 bits it is designed for supporting ‘40’ number of two address instructions, ‘400' number of one address instructions. The maximum number of zero address instructions that can be formulated is
Kartavya Kothari
asked
in
CO and Architecture
May 11, 2018
by
Kartavya Kothari
1.0k
views
ace-test-series
co-and-architecture
instruction-format
2
votes
3
answers
40
ISRO2018-6
A data driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execution. Consider the following pseudo-code: Multiply $E$ by $0.5$ to get $F$ Add $A$ and $B$ to get $E$ Add $B$ with $0.5$ to get ... sequence of execution is valid? B, C, D, A, E C, B, E, A, D A, B, C, D, E E, D, C, B, A
Arjun
asked
in
CO and Architecture
Apr 22, 2018
by
Arjun
3.1k
views
isro2018
co-and-architecture
instruction-format
2
votes
5
answers
41
ISRO2018-31
A byte addressable computer has a memory capacity of $2$^{m}$KB$ ($k$ bytes) and can perform $2$^{n}$ operations. An instruction involving $3$ operands and one operator needs maximum of: $3m$ bits $3m + n$ bits $m + n$ bits none of the above
Arjun
asked
in
CO and Architecture
Apr 22, 2018
by
Arjun
4.1k
views
isro2018
co-and-architecture
instruction-format
66
votes
7
answers
42
GATE CSE 2018 | Question: 51
A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{- byte}$ instruction format. There are four categories of ... $\text{(1F)}.$ The maximum value of $\text{N}$ is _________.
gatecse
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in
CO and Architecture
Feb 14, 2018
by
gatecse
24.2k
views
gatecse-2018
co-and-architecture
machine-instruction
instruction-format
numerical-answers
2-marks
5
votes
1
answer
43
Addresing mode
Please Explain in detail
Shubham Kumar Gupta
asked
in
CO and Architecture
Jan 16, 2018
by
Shubham Kumar Gupta
620
views
addressing-modes
co-and-architecture
instruction-format
1
vote
1
answer
44
zero address instruction
In a 16 bit computer instruction format, the size of address field is 5 bits. The computer uses expanding opcode technique. It has two 2-address instructions and 1024 one address instruction. How many zeroaddress instruction can be formulated?
Jaspreet Kaur Bains
asked
in
CO and Architecture
Jan 2, 2018
by
Jaspreet Kaur Bains
371
views
co-and-architecture
instruction-format
4
votes
2
answers
45
no of 0 address instructions
A hypothetical processor supports two-address, one-address and zero-address instructions. It has a 256 word memory and each instruction is 19 bits long. If there are 4 two-address instructions and 1000 one-address instructions, how many zero-address instructions are there?( Marks: 0.00 ) 5126 2048 1024 6144
Parshu gate
asked
in
CO and Architecture
Nov 16, 2017
by
Parshu gate
2.1k
views
co-and-architecture
instruction-format
2
votes
1
answer
46
addressing mode reduces no of bits?
computer uses addressing modes to reduce the number of bits in the addressing field of the instruction Can someone please explain how this statement is true? PLEASE Examples will be helpful
Rishabh Gupta 2
asked
in
CO and Architecture
Nov 5, 2017
by
Rishabh Gupta 2
1.7k
views
addressing-modes
instruction-format
1
vote
1
answer
47
Register Direct and Indirect Addressing Mode
I am watching IIT Madras lecture of Addressing mode, in that Prof take an example, in which we have a register r0 = 1000 Link:- https://www.youtube.com/watch?v=p9wxyIx-j-c&index=12&list=PLQObLunIEgaQ7Drxp8yCmsJqidgSsTqlw Time :- 05 ... to IIT Madras Prof it should be Register DIrect mode. which one among these are true or something I am missing.
Shubhanshu
asked
in
CO and Architecture
Sep 26, 2017
by
Shubhanshu
2.5k
views
addressing-modes
co-and-architecture
instruction-format
16
votes
5
answers
48
#ADDRESS INSTRUCTION
Consider the hypothetical processor is supports both 2 address and one address instructions.It has 128 word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported. A)1 to ... 2-address instructions are already existed.How many one address instructions can be supported ? A)128 B)2 C)256 D)32
junaid ahmad
asked
in
CO and Architecture
Jul 24, 2017
by
junaid ahmad
16.6k
views
co-and-architecture
cache-memory
machine-instruction
instruction-format
computer-architecture
2
votes
1
answer
49
Addressing mode
Self reallocating code required for displacement addressing mode.How ?Please someone explain this concept.
set2018
asked
in
CO and Architecture
Jul 17, 2017
by
set2018
1.4k
views
self-doubt
co-and-architecture
addressing-modes
instruction-format
0
votes
1
answer
50
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 30
Consider a hypothetical processor that supports two address, one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is placed in $1$ word of memory (memory ... one address instructions. The total number of zero address instructions formulated is ________ (put in integers only)
Bikram
asked
in
CO and Architecture
May 27, 2017
by
Bikram
340
views
tbb-coa-2
numerical-answers
co-and-architecture
instruction-format
0
votes
1
answer
51
Test by Bikram | Mock GATE | Test 4 | Question: 50
A computer has $170$ different operations. Memory is word addressable where word size is $4$ bytes and each instruction requires one word. All instructions have two addresses – one for register and one for memory. If there are $37$ registers, then what is the memory size? $256\; MB$ $32\; MB$ $18\; MB$ $1\; MB$
Bikram
asked
in
CO and Architecture
May 14, 2017
by
Bikram
425
views
tbb-mockgate-4
co-and-architecture
instruction-format
2
votes
1
answer
52
Test by Bikram | Mock GATE | Test 4 | Question: 12
A machine has $24$ $bit$ instruction format. It has $32$ registers and each of which is $32$ $bits$ long. It needs to support $49$ instructions. Each instruction has two register operands and one immediate operand. If ... operand is signed integer represented in $2${}'$s$ complement form, the minimum value of immediate operand is _________.
Bikram
asked
in
CO and Architecture
May 14, 2017
by
Bikram
391
views
tbb-mockgate-4
numerical-answers
co-and-architecture
instruction-format
27
votes
3
answers
53
GATE CSE 1988 | Question: 2-ii
Using an expanding opcode encoding for instructions, is it possible to encode all of the following in an instruction format shown in the below figure. Justify your answer. ...
go_editor
asked
in
CO and Architecture
Dec 11, 2016
by
go_editor
4.0k
views
gate1988
normal
co-and-architecture
instruction-format
descriptive
0
votes
1
answer
54
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 27
The memory unit of a computer has $256$ K words of $32$ bits each. The computer has an instruction format with four fields: an operation code field, a mode field (to specify one of seven addressing modes), a register address field (to ... Register address Memory address $6,5,3,18$ $5,6,3,18$ $5,18,6,3$ $5,3,6,18$
Bikram
asked
in
CO and Architecture
Nov 25, 2016
by
Bikram
262
views
tbb-coa-1
co-and-architecture
instruction-format
1
vote
3
answers
55
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 22
Consider a hypothetical processor that supports two addresses -- one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is placed in $1$ word of ... instructions and $1984$ one address instructions, then the total number of zero address instructions formulated are _______.
Bikram
asked
in
CO and Architecture
Nov 25, 2016
by
Bikram
429
views
tbb-coa-1
co-and-architecture
instruction-format
numerical-answers
2
votes
3
answers
56
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 20
A computer has $32$ bit instructions and $12$ bit addresses. If there are $250$ two-address instructions, the number of one-address instructions that can be formulated are ______.
Bikram
asked
in
CO and Architecture
Nov 25, 2016
by
Bikram
622
views
tbb-coa-1
co-and-architecture
numerical-answers
instruction-format
1
vote
1
answer
57
What is the Difference ?
Differentiate between 3 address instruction format and 3 address codes
PEKKA
asked
in
CO and Architecture
Nov 2, 2016
by
PEKKA
543
views
instruction-format
7
votes
2
answers
58
Addressing mode
What is the number of instrunctions needed to add n numbers in one address mode and store the result in the memory, assuming each number is already loaded in register? (A) n (B) n+1 (C) n-1 (D) 2n
Rakesh K
asked
in
CO and Architecture
Oct 30, 2016
by
Rakesh K
2.4k
views
co-and-architecture
addressing-modes
instruction-format
5
votes
1
answer
59
UGC NET CSE | December 2013 | Part 3 | Question: 50
Which of the following is a design criteria for instruction formats? The size of instructions The number of bits in the address fields The sufficient space in the instruction format to express all the operands desired All of these
go_editor
asked
in
CO and Architecture
Jul 29, 2016
by
go_editor
1.9k
views
ugcnetcse-dec2013-paper3
co-and-architecture
instruction-format
2
votes
2
answers
60
UGC NET CSE | June 2013 | Part 3 | Question: 42
Computers can have instruction formats with only two address and three address instructions only one address and two address instructions only one address, two address and three address instructions zero address, one address, two address and three address instructions
go_editor
asked
in
CO and Architecture
Jul 17, 2016
by
go_editor
1.8k
views
ugcnetcse-june2013-paper3
co-and-architecture
assembly
instruction-format
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