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Recent questions tagged multiplexer

3 votes

2 answers

61

ISRO2020-10
Following Multiplexer circuit is equivalent to Sum equation of full adder Carry equation of full adder Borrow equation for full subtractor Difference equation of a full subtractor

Satbir asked in Digital Logic Jan 13, 2020

by Satbir

2.7k views

0 votes

0 answers

62

Morris Mano Edition 3 Exercise 5 Question 31 (Page No. 200)
specify the size of a ROM ( Number of words and number of bits per words) that will accommodate the truth table for the following combinational circuit components: A binary multiplexer that multiplies two 4-bit numbers. A 4- ... to-1 line multiplexer with common select and enable inputs. A BCD-to-seven-segment decoder with an enable input.

ajaysoni1924 asked in Digital Logic Apr 4, 2019

by ajaysoni1924

1.1k views

1 vote

1 answer

63

Morris Mano Edition 3 Exercise 5 Question 28 (Page No. 200)
Implement the following boolean function with $4 \times 1$ multiplexer and external gates, connect A and B to selection lines. The input requirement for the four lines will be a function of C and D. These values are obtained by expressing F as a function ... be implemented with the external gates. $F(A,B,C,D) = \sum(1,3,4,11,12,13,14,15)$

ajaysoni1924 asked in Digital Logic Apr 3, 2019

by ajaysoni1924

863 views

0 votes

0 answers

64

Morris Mano Edition 3 Exercise 5 Question 27 (Page No. 200)
An $8 \times 1$ multiplexer has inputs A,B and C connected to the selection inputs $s _2,s _1$ and $s _0$ respectively.The data inputs $I _0$ through $I _7$ are as follows: $I _1 = I _2 = I _7 = 0$; $ I _3 = I _5 = 1$; $ I _0 = I _4 = D$; and $I _6 = D’$.Determine the boolean function that the multiplexer implements.

ajaysoni1924 asked in Digital Logic Apr 3, 2019

by ajaysoni1924

309 views

0 votes

0 answers

65

Morris Mano Edition 3 Exercise 5 Question 25 (Page No. 200)
Implement a Full adder with two $4 \times 1$ multiplexers.

ajaysoni1924 asked in Digital Logic Apr 3, 2019

by ajaysoni1924

191 views

0 votes

1 answer

66

Morris Mano Edition 3 Exercise 5 Question 23 (Page No. 200)
Construct a $16 \times 1$ multiplexer with two $8 \times 1$ and one $ 2 \times 1$ multiplexers.use the block diagram for the three multiplexers.

ajaysoni1924 asked in Digital Logic Apr 3, 2019

by ajaysoni1924

341 views

0 votes

0 answers

67

Morris Mano Edition 3 Exercise 5 Question 22 (Page No. 200)
Draw the logic diagram of a dual 4-to-1 line multiplexer with common selection inputs and a common enable input.

ajaysoni1924 asked in Digital Logic Apr 3, 2019

by ajaysoni1924

407 views

0 votes

1 answer

68

Multiplexer
what is the Minimum number of 21 multiplexers required to realize the following function Assume that inputs are available only in true and Boolean constants 1 and 0 are available. Shouldn't the answer be 1 ??

s_dr_13 asked in Digital Logic Mar 10, 2019

465 views

1 vote

2 answers

69

Multiplexer
Consider the given function F(A,B,C,D) = Σm(2,3,5,6,8,9,11,14) then what is the value connected at input I1 in the figure shown below if the select lines are connected to B & D respectively?

s_dr_13 asked in Digital Logic Mar 10, 2019

1.1k views

0 votes

2 answers

70

Digital logic
plz tell how it take common B’ and B

Rackson asked in Digital Logic Jan 9, 2019

309 views

1 vote

1 answer

71

DIgital MUX GFG TEST

muthu kumar asked in Digital Logic Jan 7, 2019

648 views

0 votes

0 answers

72

UPPCL AE 2018:62
Let $\text{MXI}$ be an inverting $2:1$ multiplexer whose output is $a’,$ when $s=0$ and output is $b’$ when $s=1.$ That is, $\text{MXI}(s,a,b) = s’a’ + sb’.$ What function is the following circuit equivalent to? Exclusive $\text{OR}$ Exclusive $\text{NOR}$ Inclusive $\text{OR}$ Half adder sum

admin asked in Digital Logic Jan 5, 2019

by admin

257 views

0 votes

0 answers

73

Digital Logic Made Easy
A 2-to-1 multiplexer having a switching delay of 1 μs is connected as shown in the figure. The output of the multiplexer is tied to its own select input S. The input which gets selected when S = 0 is tied to 1 and the input that gets selected when S= 1 is tied to 0. The output V0 will be 0 1 Pulse train of frequency 0.5 Mhz Pulse train of frequency 1.0 Mhz

Sambhrant Maurya asked in Digital Logic Jan 3, 2019

by Sambhrant Maurya

2.2k views

0 votes

0 answers

74

MadeEasy WorkBook: Digital Logic - Multiplexer
Why In' is taken as A'B'C'D'?

Jyoti Kumari97 asked in Digital Logic Dec 29, 2018

by Jyoti Kumari97

533 views

0 votes

0 answers

75

MadeEasy WorkBook: Digital Logic - Multiplexer
Can any explain the output function F? According to me F=(Z'C'+Z'C)

Jyoti Kumari97 asked in Digital Logic Dec 29, 2018

by Jyoti Kumari97

546 views

0 votes

0 answers

76

MadeEasy WorkBook: Digital Logic - Multiplexer
Can anyone explain this.??

Jyoti Kumari97 asked in Digital Logic Dec 29, 2018

by Jyoti Kumari97

361 views

0 votes

0 answers

77

Digital Logic: GATE-ECE-2016
answer is 6 but I’m getting 5(delay of NOR gate+delay of 1st MUX+delay of 2nd MUX)=2+1.5+1.5=5 ns where is extra 1 ns delay coming from?

aditi19 asked in Digital Logic Nov 25, 2018

1.6k views

0 votes

0 answers

78

digital logic
....

Gurdeep Saini asked in Digital Logic Nov 19, 2018

by Gurdeep Saini

447 views

1 vote

0 answers

79

Gateforum Test Series: Digital Logic - Multiplexer
Can anyone explain briefly i was unable to understand

nag.swarna asked in Digital Logic Nov 16, 2018

417 views

1 vote

1 answer

80

Gateforum Test Series: Digital Logic - Multiplexer
The answer is given B. Please explain the approach.

Gupta731 asked in Digital Logic Nov 7, 2018

1.1k views

3 votes

1 answer

81

MadeEasy Full Length Test 2018: Digital Logic - Multiplexer
If A and B are connected to the select lines of the MUX circuit, then the min-terms of the boolean function recognized by the circuit are _____ ?

kapilbk1996 asked in Digital Logic Nov 1, 2018

1.3k views

0 votes

0 answers

82

cache memory doubt
#CO Suppose Cache memory with K way set associative mapping,with no. of set -S,no. of line -L,size of each line -O. so what is hardware requirement (i.e.No.of multiplexer ,size of each multiplexer,no.of comparator,and size of each comparator) ?

Tanmay_Jawkhede asked in CO and Architecture Oct 20, 2018

by Tanmay_Jawkhede

210 views

0 votes

2 answers

83

Set associative mapping
What is the number of multiplexers required in set associative mapping hardware ? Given set bits are S, tag bits are T and word bits are W.

Alakhator asked in CO and Architecture Oct 19, 2018

676 views

1 vote

0 answers

84

Multiplexer Circuit Output
A 8x1 MUX is used to realize a four variable function, F(A,B,C,D) = Sigma M(0,2,4,6,7,9,14,15). A is LSB which is the input to the MUX. In select lines B is the MSB and D is the LSB THEN input to the MUX From Io to i7 is : A. A' A A' 0 A 0 1 1 B. A A A' 0 A 0 1 1 C. A' A' A 0 A 0 1 1 D. A' A A' 0 A' 0 1 1

Na462 asked in Digital Logic Oct 9, 2018

by Na462

2.4k views

1 vote

1 answer

85

Multiplexer Circuit
The average Propagation of each MUX is 25 ns.The frequency output signal Vo is ?

Na462 asked in Digital Logic Oct 9, 2018

by Na462

2.3k views

1 vote

0 answers

86

test_series
I KNOW THAT SIZE OF MUX WOULD BE 16:1 BUT AM NOT ABLE TO UNDERSTAND WHY THERE ARE 32 SUCH MUX??

Gate Fever asked in Digital Logic Oct 8, 2018

518 views

0 votes

3 answers

87

Ace Test Series: Digital Logic - Multiplexer
plz explain am not able to solve this .

Shubham Aggarwal asked in Digital Logic Sep 3, 2018

by Shubham Aggarwal

429 views

11 votes

3 answers

88

Digital Logic: Gate2016 ECE
The delays of NOR gates, Multiplexer and Inverters are 2ns, 1.5ns and 1ns respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, Then the Maximum propagation delay (in ns) of the circuit is _______________

Magma asked in Digital Logic Aug 11, 2018

by Magma

6.9k views

0 votes

2 answers

89

Output of 4 x 1 MUX
What will be the output "Y" of the mux?

Mk Utkarsh asked in Digital Logic Aug 7, 2018

886 views

0 votes

1 answer

90

PGEE sample paper
Choose the digital building blocks from the following list using which we can realize any boolean function. (A) 2-to-1 Multiplexer (B) 4-to-1 Multiplexer (C) 8-to-1 Multiplexer (D) 16-to-1 Multiplexer (E) None of the above

gauravkc asked in Digital Logic Apr 19, 2018

3.2k views

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Recent questions tagged multiplexer