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Recent questions tagged testbook-mock-test
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Testbook mock
Consider the following Synchronization mechanism implemented by Process A and Process B. Process A A1. flag_A = true; A2. while (flag_B) = = true) do nothing; A4. Execute Critical Section; A5. flag_A = false; Process B B1. flag_B = true; B2. if(flag_A = = ... 2..Mutual Exclusion 3 Both of the above 4.None of the above i am getting both but answer is ME only not progress plz check
Prince Sindhiya
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Operating System
Jan 2, 2019
by
Prince Sindhiya
187
views
testbook-mock-test
1
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1
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2
#1 Testbook Mock Test (COA - Cache Memory)
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in the second level cache. Assume miss penalty from the $L2$ cache to memory in $100$ cycles. The hit time of $L2$ cache is $20$ ... $10$ $5$ $15$ $\text{None of these}$
rfzahid
asked
in
CO and Architecture
Mar 15, 2018
by
rfzahid
491
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testbook-mock-test
cache-memory
co-and-architecture
0
votes
1
answer
3
#2 Testbook Mock Test(DM - Propositional Logic)
Consider the following set of propositions: I. I carry an umbrella only if it rains. II. If I carry an umbrella I use it. III. I get wet in rain only if I don't use umbrella. IV. It rains today. Possible conclusion is: (A) I will not get wet today. (B) I will get wet today. (C) I might get wet today. (D) None of the above.
rfzahid
asked
in
Mathematical Logic
Dec 12, 2017
by
rfzahid
873
views
propositional-logic
testbook-mock-test
discrete-mathematics
1
vote
1
answer
4
Testbook Mock Test (DM + Probability)
Ram draws an empty graph of 6 nodes and tosses a fair die for every pair of distinct nodes, if a prime number occurs he draws an edge between the respective pair otherwise he moves on without drawing edge between that pair. What is the probability that after the end of ... a randomly chosen node will have degree 2? (a) 5/16 (b) 1/2 (c) 3/8 (d) None of the above
rfzahid
asked
in
Probability
Dec 11, 2017
by
rfzahid
609
views
testbook-mock-test
discrete-mathematics
probability
4
votes
3
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5
Co doubt
A register to register machine support two address one address and zero address instruction. Instruction register size is 24bits and register set size is 480. If there are 48 two address instruction and 2048 zero address instruction then what is the maximum possible number of one address instruction?
Surya Dhanraj
asked
in
CO and Architecture
Oct 23, 2017
by
Surya Dhanraj
1.6k
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co-and-architecture
testbook-mock-test
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