Recent activity by PRG1499 / GATE Overflow for GATE CSE

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INSERTION IN AVL
Which of the following is highest upper bound that represents the time complexity of inserting an object into AVL tree with n-nodes. It must be 0(logn) right. What would be answer if it asked that element is continuously inserting in to a AVL tree.

Which of the following is highest upper bound that represents the time complexity of inserting an object into AVL tree with n-nodes.It must be 0(logn) right.What would be...

2.0k views

commented Feb 9, 2020

11 answers

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GATE CSE 2014 Set 1 | Question: 12
Consider a rooted n node binary tree represented using pointers. The best upper bound on the time required to determine the number of subtrees having exactly $4$ nodes is $O(n^a\log^bn)$. Then the value of $a+10b$ is __________.

Consider a rooted n node binary tree represented using pointers. The best upper bound on the time required to determine the number of subtrees having exactly $4$ nodes is...

24.4k views

commented Feb 5, 2020

5 answers

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GATE CSE 2012 | Question: 29
Let $G$ be a weighted graph with edge weights greater than one and $G'$ be the graph constructed by squaring the weights of edges in $G$. Let $T$ and $T'$ be the minimum spanning trees of $G$ and $G'$, respectively, with total weights $t$ ... $t' < t^2$ $T' \neq T$ but total weight $t' = t^2$ None of the above

Let $G$ be a weighted graph with edge weights greater than one and $G'$ be the graph constructed by squaring the weights of edges in $G$. Let $T$ and $T'$ be the minimum ...

16.5k views

commented Dec 15, 2019

1 answer

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Doubt on associativity
Does increasing cache associativity decreases conflict misses?

Does increasing cache associativity decreases conflict misses?

222 views

answered Nov 11, 2019

4 answers

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GATE CSE 2005 | Question: 68
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$

A $5$ stage pipelined CPU has the following sequence of stages:IF – instruction fetch from instruction memoryRD – Instruction decode and register readEX – Execute: ...

46.4k views

commented Nov 5, 2019

8 answers

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GATE CSE 2005 | Question: 65
Consider a three word machine instruction $\text{ADD} A[R_0], @B$ The first operand (destination) $ A[R_0] $ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) $ @B $ uses indirect addressing mode. $A$ and $B$ ... (first operand). The number of memory cycles needed during the execution cycle of the instruction is: $3$ $4$ $5$ $6$

Consider a three word machine instruction$\text{ADD} A[R_0], @B$The first operand (destination) $“A[R_0]”$ uses indexed addressing mode with $R_0$ as the index regist...

34.3k views

commented Nov 5, 2019

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true