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1
DMA Concept
reference to this pdf :https://gateoverflow.in/?qa=blob&qa_blobid=13639721099184478126 Can any one define in simple terms X μsec =data transfer time or preparation time (words/block) ? Y μsec =memory cycle time or cycle time or transfer time (words/block) ?
commented
in
CO and Architecture
Jan 26, 2019
3.9k
views
co-and-architecture
1
answer
2
static single assignment
# of temporary variable required to create 3 address code in static single assignment form for the expression P+Q*R-S/(Q*R).
commented
in
Compiler Design
Jan 22, 2019
922
views
compiler-design
intermediate-code
three-address-code
static-single-assignment
numerical-answers
0
answers
3
self doubt
While calculating the output of a MUX, select lines are MSB or LSB in expression (S1S0I0 or I0S1S0 or S1I0S0)? say F(A,B,C)=minterms{1,3,5,6} is a function implemented using mux and AC is select lines. Where does select lines and inputs to mux lies in expression (in LSB or LSB)
asked
in
Digital Logic
Jan 21, 2019
155
views
0
answers
4
Multiplexer Circuit Output
A 8x1 MUX is used to realize a four variable function, F(A,B,C,D) = Sigma M(0,2,4,6,7,9,14,15). A is LSB which is the input to the MUX. In select lines B is the MSB and D is the LSB THEN input to the MUX From Io to i7 is : A. A' A A' 0 A 0 1 1 B. A A A' 0 A 0 1 1 C. A' A' A 0 A 0 1 1 D. A' A A' 0 A' 0 1 1
commented
in
Digital Logic
Jan 21, 2019
2.4k
views
digital-logic
digital-circuits
multiplexer
2
answers
5
GATE Overflow | Mathematics | Test 1 | Question: 25
A 6 digit number 123ABC is exactly divisible by $5,7$ and $9$. How many such possible numbers are there ? 2 3 4 5
commented
in
Combinatory
Jan 19, 2019
621
views
go-mathematics-1
combinatory
quantitative-aptitude
1
answer
6
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 29
Suppose in a system we store data using arrays, we have $2$ arrays A1 and A2. Array A1 contains $256$ elements of size $4$ bytes each. The first element is stored at physical address $4096$ ... of bytes that will be written to memory during execution of the loop is : $256$ $1$ $0$ $2048$
commented
in
CO and Architecture
Jan 9, 2019
541
views
tbb-coa-2
co-and-architecture
cache-memory
14
answers
7
GATE CSE 2008 | Question: 67
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as ... tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$
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in
Operating System
Dec 11, 2018
76.2k
views
gatecse-2008
operating-system
virtual-memory
normal
1
answer
8
Ace bits and bytes
Is $(aa)^*$ +a$(aa)^*$ = a*?
asked
in
Theory of Computation
Nov 25, 2018
472
views
regular-expression
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