Test by Bikram | Mock GATE | Test 3 | Question: 24

Question

A $4-bit$ carry-lookahead adder adds two $4-bit$ numbers. The adder is designed only using $AND, OR, NOT, NAND $ and $NOR$ gates. We assume that all the inputs are available in both complemented and uncompleted forms. The delay of each gate is $one$ time unit if we assume that the carry network has been implemented using two-level $AND-OR$ logic.

Thus, the overall propagation delay of the adder is ______  in terms of time units.

Answer 1

gate delay for generate and propagate functions of each level.
C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1C_in

Thus, for calculation of each of the carry outs, we need 2 gate delays after generate and propagate are calculated.

Calculation of sum using AND-OR circuit requires calculation of NOT of each of the carry bits.
This takes 1 gate delay. The AND-OR circuit takes 2 more gate delays.

Total gate delays = 1 + 2 + 1 + 2 = 6 gate delays = 6 units.

Comments

Can anybody explain .... how $P_i$ is calculated in $1$ gate delay

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for better understanding- https://gateoverflow.in/1057/gate2004-62

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If we use $P_i = A_i \oplus B_i$, so that we can reuse it later in the sum equation, then calculation of $P_i$ takes two $2$ delays at the beginning, not $1$. So shouldn’t this be $7$ delays?