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Consider the following program to be executed on this processor:
I1: Load R1, A /R1 ← Memory (A)/
I2: Add R2, R1 /R2 ← (R2) + R(1)/
I3: Add R3, R4 /R3 ← (R3) + R(4)/
I4: Mul R4, R5 /R4 ← (R4) + R(5)/
I5: Comp R6 /R6 ← (R6)/
I6: Mul R6, R7 /R3 ← (R3) + R(4)/

a. What dependencies exist in the program?
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Data Dependencies exist in this program
e.g : in I2 : value of operand r1 is dependent on execution of I1 instruction 
There are no Control Dependencies in this code since there are no Transfer of Control Instructions.
Structural dependencies will depend on stages of this pipelined processor whether  they are 4 or 5 what exactly each stage does 

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What does  R(1) means?
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R1 is just a register name
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