Consider an L1 cache, L2 cache, and main memory. The hit rates and hit times for each are:
70% hit rate, 5 ns hit time for L1.
90% hit rate, 14 ns hit time for L2.
100% hit rate, 150 ns hit time for main memory
If there a total of 300 memory accesses, how many of these accesses are serviced from main memory?