GATE CSE 2018 | Question: 23

Question

A $32\text{-bit}$ wide main memory unit with a capacity of $1\;\textsf{GB}$ is built using $256\textsf{M} \times 4\text{-bit}$ DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$. The time taken to perform one refresh operation is $50\;\text{nanoseconds}$. The refresh period is $2\;\text{milliseconds.}$ The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________.

Comments

Yes, it is there in CO.

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no need to watch this video

just read carl HAMACHER or peter linz, RAM refreshing is best explained there.

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RAM refreshing in Peter Linz ?

Answer 1

One refresh operation takes $50\;\text{ns}$.

Total number of rows $= 2^{14}$

Total time to refresh all Rows $= 2^{14}\times 50\; \text{ns} = 819200 \;\text{ns} =  0.819200\;\text{ms}$
The Refresh Period is $2\;\text{ms}.$

$\%$ Time spent in refresh  $= \frac{\text{Total time to Refresh all Rows}}{\text{Refresh period}}\ast 100
$
                                             $= \frac{0.8192\;\text{ms}}{2.0\;\text{ms}}\ast 100 = 40.96\%$

$\%$ Time spent in Read/Write $= 100 - 40.96 = 59.04\%$

$= 59\%$ (Rounded to the closest Integer)

Reference: https://en.wikipedia.org/wiki/Memory_refresh

Comments

@Dheeraj3859 No. Exactly One row is refreshed at a time

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Why do we have to consider the $2^{14}$ rows? Why can’t we simply take (20ms-50ns) for one refresh cycle in which 19.5 ms we get as read write time. i.e 97.5% ???

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@Mrityudoot Refresh operation time of 50ns is for one row,so to refresh entire chip we have do 2^14 * 50ns.

All the chips get refreshed parallely so no need to count for each chip.

Answer 2

On a 32bit machine, the maximum amount of memory is around 4GB and it's ok to have a capacity of less than 4GB. Because it depends on OS as well and might be less due to parts of address space being reserved, So the usable capacity of the main memory is 1GB, and this main memory may have been designed using more than 1 DRAM chips, 
One DRAM chip size is 256M x 4bits=2^28 x 2^2 =2^30bits.
No. of DRAM chips needed to design main memory of size 1GB= 2^30*8 / 2^30=8. so 8 DRAM chips are needed. Now there are 2^14 rows in each DRAM chips. then how many cells(column) are there in one row or in one DRAM chip=2^30bits(Size of one DRAM) / 2^14=2^16.
The time taken to perform one refresh operation is for only 1 row of 1 DRAM chip and it is 50nsec. The refresh period is 2 msec means after every 2msec the DRAM chips need to be refreshed otherwise data stored in it will get lost. Now they are asking what is the percentage of time for meaningful operations(R/W) other than refresh overhead. so if we calculate refresh overhead itself, we can also derive percentage of time for meaningful operations(100%- refresh overhead%).
 Given, the total number of rows is 2^14 and time taken to perform one refresh operation is 50 nanoseconds. So, total time taken to perform refresh operation on 1DRAM chip = 2^14*50 nanoseconds = 819200 nanoseconds = 0.819200 milliseconds. But the refresh period is 2 milliseconds.

Note:- All DRAM chips are refreshed simultaneously.

So, time spent in refresh period in percentage or REFRESH OVERHEAD= TIME TAKEN FOR 1 REFRESH OPERATION TO 1 DRAM CHIP / REFRESH INTERVAL 

= (0.819200 milliseconds) / (2 milliseconds) = 0.4096 = 40.96% Hence, time spent in read/write operation = 100% - 40.96% = 59.04% = 59 (in percentage and rounded to the closet integer). So, answer is 59.

Comments

@Nitesh Singh 2 

I think the below statement you made is wrong.

On a 32bit machine, the maximum amount of memory is around 4GB

The maximum amount of memory actually depends on the address bus size. We always address words. We also call each word as a cell. 

Word size = 32 bits in a 32-bit machine and data bus has 32 lines to carry 32 bits of data.

Word size = 64-bits in a 64-bit machine and data bus has 64 lines to carry 64 bits of data.

Ex: Say I have a 32-bit machine and 8 GB RAM. That means we will have $\frac{8GB}{32 bits}$ = $\frac{2^{33}B}{2^{2}B}$ = $2^{31}$ words.

So, the address bus will need to have 31 lines to carry 31 bit address.

In question it has been given:

A 32-bit wide main memory unit with a capacity of 1GB is built using 256 M $\times$ 4-bit DRAM chips.

It means that word width = 32 bits. Number of such 32 bit words that can fit in 1GB RAM = $\frac{2^{30}Bytes}{32 bits} = \frac{2^{30}}{2^{2}} = 2^{28}$ words. Therefore we will need 28-bits to address each word in this RAM.

256 M $\times$ 4-bit, this means that there are 256 M cells each of which contains a word of 4-bit length. Size of such D-RAM chip = 256 M $\times$ 4-bit = $2^{30}$ bits = $2^{27}$ Bytes.

Now we need to build a RAM of size 1GB = $2^{30}$Bytes using D-RAM chip of size 256 M $\times$ 4-bit = $2^{27}$ Bytes.

Clearly we will need 8 such 256 M $\times$ 4-bit D-RAM chips.

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Sorry to say but you are wrong.

http://www.mathcs.emory.edu/~cheung/Courses/255/Syl-ARM/4-intro/bus-width.html

Clearly mentioned in the above link that:

• Each wire of the address bus can convey (= transfer) 1 bit of the address

  Therefore:

   

  An address bus that contains n wires can convey n bits

   

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• Each memory byte is identified by a unique memory address !!!

  So:

   

  A address bus that consists of 8 wires (= bits), can convey 28 (= 256) different addresses   A address bus that consists of 16 wires (= bits), can convey 216 (= 64K) different addresses     The Apple II PC has a 16 bit address bus and has maximum 64 K byte RAM memory Wikipedia: click here   A address bus that consists of 24 wires (= bits), can convey 224 (= 16M) different addresses     A address bus that consists of 32 wires (= bits), can convey 232 (= 4G) different addresses     If your PC has 8 G byte memory, then your PC has an address bus that contain at least 33 wires (bits) because 233 = 8,589,934,592 (~= 8 × 109 = 8 G byte)

 

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NiteshSingh2

The refresh period is 2 msec means after every 2msec the DRAM chips need to be refreshed otherwise data stored in it will get lost

 this refresh period also includes the time for read/write right?

Answer 3

Time taken to refresh one row = 50 ns
There are 2^14 rows, so time taken to refresh all the rows = 2^14 * 50ns = 0.82 milliseconds
It is given that total refresh period is 2ms. The refresh period contains the time to refresh all the rows and also the time to perform read/write operation.
So % time spent in refresh = (Time taken to refresh all rows / refresh period)*100
= (0.82 ms / 2ms)*100
= 41%
So the % of time for read/write operation = 100 - 41 = 59%