An address sequence S experiences 100 compulsory cache misses. The sequence S experiences 500 misses when it is passed through a 32 KB fully-associative cache. The sequence S experiences 1000 misses when it is passed through a 32 KB 8-way set-associative cache. The number of conflict misses that the sequence S experiences when it is passed through a 32 KB 8-way set-associative cache is___?
