In the diagram above, the inverter (NOT gate) and the AND-gates labeled $1$ and $2$ have delays of $9, 10$ and $12$ nanoseconds (ns), respectively. Wire delays are negligible. For certain values $a$ and $c$, together with certain transition of $b$, a glitch (spurious output) is generated for a short time, after which the output assumes its correct value. The duration of glitch is:
The output of AND gate 1 will be available at the input of OR gate after 9+10 = 19 nanoseconds but Output of AND gate 2 will be available after 12 nanoseconds only. So a glitch will be generated for 19-12 = 7 nanoseconds after which the output assumes its correct value. Option A is correct.
since here OR gate delay is not given ...so take its delay as zero..
option (A)
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