Gate forum workbook

Question

We are Simulate a cache of 16 words, 2-way set associate cache with 2 word cache lines and LRU replacement policy; assume the cache in initially empty. The following sequences of address references are generated (the addresses are given in hexadecimal), where all references are instruction or data fetches (no stores):
62 63 64 98 65 99 66 99 67 68 69 6A 63 64 108 65 109 66 109 67 68 69 63

After 8 memory references, which one the following is correct regarding the status of cache?

(A) Set 1 contains 63

(B) Set 0 contains 64

(C) Both (A) and (B)

(D) None of these

After 12 memory references, which one the following is correct regarding the status of cache?

(A) Set 1 contains 6A

(B) Set 0 contains 64

(C) Both (A) and (B)

(D) None of these

After 15 memory references, which one the following is correct regarding the status of cache?

(A) Set 1 contains 6A

(B) Set 0 contains 108

(C) Both (A) and (B)

(D) None of these

Comments

1(a)

2(a)

3(c)

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Solution: a), a), c)

bits to check for set = 2

so if it is 64 then it can be written as 0110 0100 - those highlighted 2 bits represents set id, where that number belongs.

Answer 1

Answer for 1 is B