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  S1 S2 S3 S4
I1: 1 2 1 2
I2: 2 1 2 1
I3: 1 1 2 1
I4: 2 1 2 1

 

Consider a pipeline processor with 4 stages S1 to S4. We want to execute the following loop

for (i = 1; i < = 10; i++) 
    {I1, I2, I3, I4}

The output of  I1 for i = 2 will be available after

  1. 11 ns
  2. 12ns
  3. 13 ns
  4. 28 ns
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4 Comments

Hemanth_13 please explain reasons for 8th cycle of i=1 in 2nd loop.

i kind of know concept but not sure

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Instead of stall if I would have written s2 there I1's S2 might be picked by S3 stage rather than I4's to avoid this confusion the S2 is delayed for a cycle.
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