First, the address bus takes us to the desired cache-line in cache (this will take 2.5 ns including the search time). If there is a miss this means the required word is not present in the respective cache-line, but keep in mind that we are already on this cache-line and we are just waiting for the block to be arrived on this line.. Now when required block will be transferred (this will take memory access time i.e. 50ns + 15*5 ns) then the required word will be on that line on which we are already standing. Now we will just take the desired word through data bus. Thus, there will be no need to access the cache twice. Also since in question they haven't mentioned the WRITE OPERATION TIME in cache and not also the COPYING DELAY, so we'll just ignore these delays.
And keep in mind, that there are various methods for hierarchical access. It varies from book to book. This question doesn't explain detailed scenario. Don't panic. In Gate exam. they will clearly describe the scenario and they will also advise to ignore some delays accordingly in the question.