MadeEasy Workbook: Digital Logic - Adder

Question

x and y are two n bit numbers. these numbers are added by n bit carry look ahead adder which uses k logic levels. if the average gate delay of carry look ahead adder is d then what will be the maximum Delay of carry look ahead adder circuit?

1. N2
2. Kd
3. Nkd
4. Nd

Comments

Option 2??

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Yes, but how you got it?

Answer 1

carry look ahead adder addition doesn't depend on no. of bits , it depends on no. of levels

Answer 2

We are using k-levels of carry look-ahead adder. For example,

Suppose we have 16 bits numbers to add and 4 bit carry look-ahead adder, then we’ll need 2 levels of carry look-ahead adder to compute all the carries.

 

$Level-2\rightarrow\:\: |\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:Generator 5\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:\:|$

$Level-1\rightarrow \: \: |\:generator4\:|\:generator 3\:|\:generator 2\:|\:generator 1|$

$Level-0\rightarrow \: \: |a_{15}a_{14}a_{13}a_{12}|\: \: a_{11}a_{10}a_{9}a_{8}\: |\: \: \: a_{7}a_{6}a_{5}a_{4}\: \: \: |\: \: a_{3}a_{2}a_{1}a_{0}\: \:\:\:|$

 

Also, each level’s carry generator can work in parallel. Therefore, each level causes ‘d’ delay. And therefore, total delay = k*d.