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#madeeasy test series
Soumya Tiwari
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Dec 12, 2018
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co-and-architecture
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operand-forwarding
Soumya Tiwari
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Dec 12, 2018
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Ashutosh_Mishra
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Dec 12, 2021
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GATE appliedroots test series
I have 3 doubts in the following solution: Doubt 1: In red colour While I1 is in the Memory-access stage, how can I4 fetch the instruction from the memory? Isn't this a structural dependency problem? Doubt 2: In blue ... operate with register only so the memory-access stage shouldn't happen for these instructions, correct? Solution as per my understanding:
Ashutosh_Mishra
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Dec 12, 2021
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Ashutosh_Mishra
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aditya dhanraj
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CO and Architecture
Jan 13, 2019
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Test series
#Pipelining Please clear my doubt. In a 5 stage pipelining (IF, ID, EX, MA, WB) there are 5 instruction given. Instruction 1 : R2 ← R0 + R1; Instruction 2 : R1 ← R2 - R1; Instruction 3 : R0 ← R2 - R0; Instruction 4 : R2 ← ... My understanding is whenever dependency is there b/w instruction, ID phase of Next instruction will occur after EX phase of previous Instruction. It is correct ?
aditya dhanraj
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aditya dhanraj
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Markzuck
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Dec 25, 2018
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MadeEasy Test Series: CO & Architecture - Pipelining
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)
Markzuck
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Markzuck
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Na462
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Oct 13, 2018
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MadeEasy Test Series: CO & Architecture - Pipelining
The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction output present at 4th stage and ALU instruction output is at third stage. Assume each stage ... must be inserted to achieve CPI = 1 by using Operand Forwarding ? A. 3 B. 4 C. 5 D. 6
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