We usually use the formula that Speedup = $\frac{\text{Pipeline Depth}}{\text{CPI_{ideal} + Pipeline Stalls Per Instruction}}$.
Now, this formula works only in the case when all the instructions pass through all the stages of the pipeline. Here, I I've assumed that all the instructions pass through all the stages, and hence wrote the numerator as five. Regarding the denominator, we take the ideal CPI of a processor to be 1 on a pipelined processor.
For the other term, assuming the stalls are only from branches, we can write the stall cycles as $\text{Branch Frequency*Branch Penalty}$. Here, the branch frequency will be $p$ and using the same, I've solved the question.
The important assumption is that CPI of a pipelined processor is $1$ only when the number of instructions are large. For a finite number of instructions, using the exact value of instructions should give a more accurate answer.