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MadeEasy Test Series: CO & Architecture - Cache Memory
Shubham Kumar Gupta
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CO and Architecture
Jan 10, 2019
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Rishi yadav
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Shubham Kumar Gupta
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CO and Architecture
Jan 10, 2019
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Rishi yadav
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Shubham Kumar Gupta
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prashant jha 1
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Jan 10, 2019
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Is it 3.6?
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Shubham Kumar Gupta
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Yes. Can you explain?
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prashant jha 1
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Out of 1000 memory accesses , 40 are miss in L1 cache . And out of those 40 , 10 misses happens in L2 cache.
So AMAT = 1 clock cycle + 40/1000[15 + 10/40 x 200]
= 1+ 0.04x15 + 0.04 x 0.25 x 200 = 3.6 clock cycles
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how you got this formula?
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AMAT = h1*t1 + (1-h1)*h2*(t1+t2) + (1-h1)(1-h2)*(t1+t2+t3)
=>$\frac{960}{1000}*1 + \frac{40}{1000}*\frac{30}{40}*(1+15) + \frac{40}{1000}*\frac{10}{40}*(1+15+200)$
=>3.6 clock cycles
Rishabh Agrawal
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Jan 10, 2019
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Shubhgupta
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just a suggestion,
use simplified formula it will take less time-
$T1+(1-H1)T2+(1-H1)(1-H2)T3$
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