MadeEasy CBT Test 2019: CO & Architecture - Cache Memory

Question

consider a computer with 4 GB main memory synchronized with CPU speed using 8-way set associative cache of 16 KB. memory system is organized into 64 word blocks and word length of CPU is 64 bits. the size of tag in cache line in the set is ______ bits.

(answer is 21)

Comments

Seems like they've taken Byte addressable and not word. With word addressable answer would be different

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@Satbir

It is not 64 blocks, the size of each block is given here which is 64 word and since word size= 8 Bytes and hence block size will be = 64 * 8 = 512 Bytes So 9 bits will be required in order to represent block offset.

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Here block size is 64 words i.e. $2^6$ words. Therefore 6 bits are required to represent block offset.

Memory is word addressable. Convert everything to words first.

Answer 1

Main Memory= 4GB=2^2 * 2^30= 2^32 Bytes

Physical Address= 32 bits

Cache size= 16KB = 2^4 * 2^10= 2^14 Bytes

Block offset= 64 word=2^6*2^3=2^9 Bytes(because word size is 64 bits)

No. of blocks=2^14/2^9= 2^5

No of sets= 2^5/2^3=2^2

Tag= 32-(2+9)= 21 bit