ME TEST

Question

A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main memory addresses (in hexadecimal). The conflict miss if 2-way set associative LRU cache is used is_____

100,108, 114,1C7, 128, 1B5, 100, 108, 1C7

I just want to know what will be the address partition look like. 

1.

tag(7)

set(1)

offset(4)

2.

tag(7)

set(1)

offset(2)

 

Comments

Why tag 19 bits? mm addresses are 3 hex bits, so mm address should be 12 bits, right?

I'm getting 7+1+4

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that was my mistake? sorry for that.

what i want to know that as we are given memory is byte addressable we should consider 7+1+4 for calculations but in ans they have used 7+1+2 {word addressable format}.