ISRO2020-6

Question

A non-pipelined CPU has $12$ general purpose registers $(R0,R1,R2, \dots ,R12)$. Following operations are supported

• $\begin{array}{ll} \text{ADD Ra, Rb, Rr} & \text{Add Ra to Rb and store the result in Rr} \end{array}$
• $\begin{array}{ll} \text{MUL Ra, Rb, Rr} & \text{Multiply Ra to Rb and store the result in Rr} \end{array}$

$\text{MUL}$ operation takes two clock cycles, $\text{ADD}$ takes one clock cycle.

Calculate minimum number of clock cycles required to compute the value of the expression $XY+XYZ+YZ$. The variable $X,Y,Z$ are initially available in registers $R0,R1$ and $R2$ and contents of these registers must not be modified.

• A. $5$
• B. $6$
• C. $7$
• D. $8$

Comments

option B ) 6 cycles xy+xyz+yz = y(x+xz+z)

Answer 1

Let's first rewrite the expression as: y*(x + z + x*z)

the instructions are:
ADD R0, R1, R3

MUL R0, R1, R4

ADD R3, R4, R3

MUL R2, R3, R3

Since it is a non-pipelined processor it will take 2*2 + 2*1 = 6 cycles

Comments

Would the answer be different if the CPU was pipelined?

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let us rewrite the equation as Y(X+Z+X*Z)

Let us consider the following instruction

ADD R0, R2, R3

MUL R0, R2, R4

ADD R3, R4, R3

MUL R1, R3, R3

So tye nos of clock cycle will be 1+2+1+2=6 clock cycles.

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Is it allowed to optimze the instruction to determine minimum number of clock cycle needed?

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got it now