Pipeline problem

Question

A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, OF and WO stages takes 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instruction, 2 clock cycles for MUL instruction and 4 clock cycles for DIV instructions respectively. The number of clock cycles needed to execute the following sequence of instruction is ________.

In the explanation they have mentioned in this way :

Now , my question is , Here I₁ and I₂ are dependent , so how can they start without any stall , no operand forwarding is also mentioned.

Comments

The answer is 16 only,what is the confusion?

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Hi , in the I3 how can we do OF when WO is not done for I2 ? Should we start OF from clock 11 ?

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that is a mstk.in I2 5,6,7 will be stall..answer is right.solve is not

Answer 1

Yes for I₂ 5,6,7 should be a stall.It should have been - or a implicit NOP[no operation] .

Comments

for I3 9,10 also be stall

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but answr is 16..make those correcion,i have told.. then pic will be right

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done !