Pipelining_ques

Question

Consider 5 stage pipeline which allow all instructions except branch instruction. Program contain 30% conditional instructions out of which 75% are branch instruction. Processor stop fetching the following instruction after the branch instruction untill target address is available. Target address is available at the end of the pipeline stage.
All the stages are perfectly balanced with 20 GHz clock time. The processor is running with rate of ____________ (in MIPS).

Comments

10526.31   , if  target address available at the end of all pipeline stages(4 stalls)..

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@Amsar pls review the below-given answer.

Answer 1

Ideal CPI = 1

CPI increase due to stall [4stalls due to branching]= 0.30*0.75*4=0.9

Throughput =Clocks per second / [IdealCPI + increase due to stall]

$\frac{20*10^{9}}{1+0.9}$ = 10526.31 * 10^6  hence 10526 MIPS

                         

Comments

yes, bahirNaik  answer should be 10526.3157 MIPS

I made mistake , thanks :)