in CO and Architecture retagged by
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in CO and Architecture retagged by
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ADD r2,@r1 => r2 is in reg direct AM, r1 is in reg-indirect AM

IF + ID => Fetch operation → 2 cycles

OF → s1 takes 1 register reference (ignore), s2 take 1 register ref (ignore) and 1 memory ref (2 cycle) → total 2 cycles

PD → processing takes 1 ALU operation → 1 cycle

WB → 1 reg ref (ignore)

Total 5 cycles.

2 Comments

But It was asked Memory Cycle na ? Actually I am bit confused between Memory cycle and Cpu cycle?
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yup… it says memory cycles… I did not read carefully. But anyway, in such questions asking for memory cycles doesn’t make much sense. Because you see… they haven’t given any information for memory cycles. Even if we want to calculate, we may assume 1 mem ref takes 1 mem cycle, answer could be 1 mem cycle. But then again, the fetching operation will also access memory, there too must be memory cycles utilized. So, question make more sense when talking about cpu cycles only.
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