pipelining hazard

Question

Consider a 5–stage pipelined processor with stages – Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MA) and Write Back (WB). All stages except Memory Access takes 1 clock cycle each for all instructions. Memory access takes 3 clock cycles for instruction LOAD. How many clock cycles are needed to execute the following sequence of instructions with optimization?

I0 : LOAD R0, 3(R1) ; R0  ←  [3 + [R1]]

I1 : ADD R2, R0, R1 ; R2 ← R0 + R1

I2 : LOAD R3, 4(R4) ; R3 ←  [4 + [R4]]

I3 : SUB R5, R3, R4 ; R5 ←  R3 – R4

 

ans is 14 bt how?

Comments

I am getting 12. I don’t think answer should be 14.

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There is a  dependency between $I_{0}$ and $I_{1}$ as the result from $I_{0}$ i.e register $R_{0}$ is used as an operand in $I_{1}$. Same type of dependency exists between $I_{3}$ and $I_{4}$.

So, if we were to use operand forwarding the answer would come out to be 12. But since it is not mentioned in question that operand forwarding is used, so pipeline will be stalled. In that case the answer would come out to be 14.

I hope this explanation makes sense.

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@rexritz it says ‘with optimization’ does that not mean that operand forwarding is used???

 

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Yes you are right. Using optimization technique like operand forwarding it should take 12 clock cycles. I would also have gotten 12 as the answer  if the user didn’t mentioned that answer was 14, which led me to think of a solution without using operand forwarding technique.

If this was asked in the exam I would have ticked 12 as the answer.

Answer 1

T1      T2      T3      T4      T5      T6       T7      T8       T9      T10      T11       T12      T13      T14

IF       ID       ID       ID       EX     MA     WB      

          IF        ...       ...        ...       ...         …         ID        EX      MA      WB

                     IF       …        ID       ID       ID         EX       MA     WB

                                 IF                                                                              ID        EX        MA       WB

so overall 14 cycle required instruction I1 is dependent on I0, we can’t used here operand forwarding so stall cycles required and as same instruction I3 is dependent on I2 so here also stalls requires

so ans is 14

Answer 2

     

1

2

3

4

5

6

7

8

9

10

11

12

13

14

I0

IF

ID

EX

MA

MA

MA

WB

I1

IF

ID

ID

ID

ID

EX

MA

WB

I2

IF

IF

IF

IF

ID

EX

MA

MA

MA

WB

I3

IF

ID

ID

ID

ID

EX

MA

WB