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An MIPS pipeline has five stages, with a clock cycle of $200 \mathrm{ps}$. Suppose that this MIPS pipeline is redesigned to have four stages, with a clock cycle of $250 \mathrm{ps}$. Assuming an infinite sequence of instructions, what speedup will this new design achieve when compared to the five-stage pipeline?
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All India Mock Test 2 - Solutions Part 3

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For the sequence of $\mathrm{N}$ instructions, the speedup of the new pipeline design would be:
$$
\text { Speedup }=\frac{1000+200 \mathrm{~(N-1)}}{1000+250 \mathrm{~(N-1)}}
$$
And, as $\text{N}$ goes to infinity, we see the limiting speedup will be $200 / 250=4 / 5=0.8$, which means the revised design described above would actually be slower.


NOTE: The answer to this question will be 0.8, Not 1.25.

I knew many students will put 1.25, that's why the speedup was asked for the slower system, not for the faster system. 

Did you make this mistake??? 

Take Care in the GATE exam.. We are here to make sure you make all silly mistakes before the GATE exam, & not in the GATE exam. 

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