Cache has a hit rate of 95%, 128 byte lines and a cache hit latency of 5 ns

Question

A cache has a hit rate of 95 percent, 128-byte lines, and a cache hit latency of 5 ns. The main memory takes 100 ns to return the first word(32 bits) of a line, and 10 ns to return each subsequent word. What is T_miss for this cache? (Assume that the cache waits until the line has been fetched into cache and then re-executes the memory operation, resulting in a cache hit. Neglect the time required to write the line into the cache once it has been fetched from main memory. Also assume that the cache takes the same amount of time to detect that a miss has occurred as to handle a cache hit.)

Comments

Cache miss penalty is asked, miss penalty is additional time spent if we get to know that it is a miss.

Additional time = Time to transfer line from memory to cache + Time to access the word from the cache.

                       = 100 + 31*10 + 5 = 415ns

Answer 1

AS the 128 byte lines are there and 32 bits( or 4 byte) words are present so,

total no .of words = 128 byte/4byte= 32

it takes 5ns to detect that cache miss has occurrred(given it last line of question)

now first word fetching time is = 100ns 

each subsequent word fetching is 10 ns(as 31 words are remaing now ) so = 31*10ns  = 310ns

total time = 310 + 100+5 = 415 ns

now this operation is re-executed as cache hit so it takes 5ns more 

415+5= 420ns

Comments

Why 5ns more needed because it is already included in 415ns??

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@Tauhin Gangwar I think @Prateek Raghuvanshi is right it should be 415ns

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@Tauhin Gangwar

What if “Assume that the cache waits until the line has been fetched into cache” was only mentioned in the question but not “Assume that the cache waits until the line has been fetched into cache and then re-executes the memory operation, resulting in a cache hit.” then we would not add 5nsec right ???

Answer 2

Tmiss = Tc + (T100 + (128-4)/4 x 10 ns) +5ns=420ns