GATE CSE 2008 | Question: 67

Question

A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows:

• Bits $30-31$ are used to index into the first level page table.
• Bits $21-29$ are used to index into the 2nd level page table.
• Bits $12-20$ are used to index into the 3rd level page table.
• Bits $0-11$ are used as offset within the page.

The number of bits required for addressing the next level page table(or page frame) in the page table entry of the first, second and third level page tables are respectively

• A. $\text{20,20,20}$
• B. $\text{24,24,24}$
• C. $\text{24,24,20}$
• D. $\text{25,25,24}$

Comments

Few more explanations:

https://web.archive.org/web/20140805205005/https://www.gatementor.com/viewtopic.php?f=251&t=4863

https://stackoverflow.com/questions/21702389/number-of-page-table-index-bits-in-multilevel-paging

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The main point to note here is $For\ each\ level\,\  page\ size/frame\ size\ depends\ on\ the\ size\ of\ page\ used\ in\ the\ next\ level\\.$

$Page\ size\ in\ multilevel\ paging\ may\ change,\ it\ need\ not\ be\ same\ in\ every\ level.$

If you understand this point you’ll able to answer the question.

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This is like the 6th time I have come back to this question because I hadn't been able to understand the solution well enough and it has been an unscratchable itch for weeks but this time I think I have succeeded in getting to the gist of the concept. I think the most important observation to be drawn here is that the page tables will not be page aligned this is why you need more bits to address page tables than the page frames themselves(because they are larger 2¹²B > 2¹¹B). I hope this is the last time I'm here. Goodluck everyone.

Answer 1

Physical address is $36$ bits. So, number of bits to represent a page frame $ = 36-12 = 24\ bits$ ($12$ offset bits as given in question to address $4$ KB assuming byte addressing). So, each entry in a third level page table must have $24$ bits for addressing the page frames. 

A page in logical address space corresponds to a page frame in physical address space. So, in logical address space also we need $12$ bits as offset bits. From the logical address which is of $32$ bits, we are now left with $32-12 = 20\ bits$; these $20\ bits$ will be divided into three partitions (as given in the question) so that each partition represents 'which entry' in the $i^{th}$ level page table we are referring to.

• An entry in level $i$ page table determines 'which page table' at $(i+1)^{th}$ level is being referred. 

Now, there is only 1 first level page table. But there can be many second level and third level page tables and "how many" of these exist depends on the physical memory capacity. (In actual the no. of such page tables depend on the memory usage of a given process, but for addressing we need to consider the worst case scenario). The simple formula for getting the number of page tables possible at a level is to divide the available physical memory size by the size of a given level page table.

$\text{Number of third level page tables possible} = \frac{\text{ Physical memory size}}{\text{ Size of a third level page table}}$
$\qquad = \frac{ 2^{36} } {\text{Number of entries in a single third level page table} \times \text{ Size of an entry} }$
$\qquad = \frac{2^{36}} {2^9 \times 4} \because \text{ (bits 12-20 gives 9 bits)}$
$\qquad = \frac{2^{36}}{2^{11}}$
$\qquad =2^{25}$

PS: No. of third level page tables possible means the no. of distinct addresses a page table can have. At any given time, no. of page tables at level $j$ is equal to the no. of entries in the level $j-1$, but here we are considering the possible page table addresses.

http://www.cs.utexas.edu/~lorenzo/corsi/cs372/06F/hw/3sol.html See Problem 3, second part solution - It clearly says that we should not assume that page tables are page aligned (page table size need not be same as page size unless told so in the question and different level page tables can have different sizes).
So, we need $25$ bits in second level page table for addressing the third level page tables.

Similarly we need to find the no. of possible second level page tables and we need to address each of them in first level page table.

Now,

$\text{Number of second level page tables possible} = \frac{\text{ Physical memory size}}{\text{ Size of a second level page table}}$
$\qquad= \frac{ 2^{36} } {\text{Number of entries in a single second level page table} \times \text{ Size of an entry} }$

$\qquad = \frac{2^{36}} {2^9 \times 4} \because \text{ (bits 21-29 gives 9 bits)}$
$\qquad= \frac{2^{36}}{2^{11}}$
$\qquad=2^{25}$

So, we need $25$ bits for addressing the second level page tables as well. 

So, answer is (D). 

Video Explanation for Multi-level Paging: https://youtu.be/bArypfVmPb8

(Edit:-
There is nothing to edit for such awesome explanation but just adding one of my comment if it is useful - comment. However if anyone finds something to add (or correct) then feel free to do that in my comment.)

Comments

All the page tables are stored in main memory which has fixed size of frames in paging architecture. When you refer to any of the page table (whether it is third level ,second level or first level) you search for it somewhere in main memory frames. And number of frames in memory decide the number of bits required to address a particular frame which is same for all the main memory frames.

My question is that when all the page tables are stored in some memory frame WHY DO WE NEED 25 BITS TO ADDRESS SOME FRAME INSTEAD OF 24 BITS ??

How can we use, at the same time, different number of bits to address different level page table DESPITE THE FACT THAT ALL OF THEM RESIDE IN ONE OR THE OTHER FRAME IN MAIN MEMORY ??

Please answer. Its completely absurd to even imagine an architecture that use different number of bits OR (more precisely) different size and number of frames for the same memory at same time !!

Thank You

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"All the page tables are stored in main memory which has fixed size of frames in paging architecture. When you refer to any of the page table (whether it is third level ,second level or first level) you search for it somewhere in main memory frames. And number of frames in memory decide the number of bits required to address a particular frame which is same for all the main memory frames."

Where are these sentences given?

It is possible to even use pages of different sizes in a system. i.e., we can change the number of OFFSET bits and correspondingly change the page size. All we need for this is the MMU (or sometimes OS) to handle the different offset sizes which is not a difficult task. 

So, in the given question, a main memory page frame is fetched with 24 bits of address and 12 offset bits, while the page frame corresponding to a third level page will be fetched using 25 bits of address and 11 offset bits (9 bits from VA + 2 bits for 4 bytes of PTE). 

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Sir, what does that mean "number of third level page tables possible"? we have only one page table at each level for a process ryt? (I mean if multilevel paging is implemented)

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"Yes a memory page can be of different size based on page offset and that will vary the number of pages that can fit in memory accordingly."

But at the same time "Is it possible for main memory to keep DIFFERENT PAGE SIZES". I mean as in this question we need different page size for third and 2nd PT , So can the memory maintain both pages in memory AT THE SAME TIME ??

My doubt is that "How can memory slots be divided such that some page is of 1KB(say) and other is of 2KB at the same time " !!!

And yes you have answered that "page frame of main memory(actual page containing instructions) is fetched using 24 bits while a third level PT (containing frame numbers for actual page residing in main memory) is 25 bits." Assume that both the actual page and third level PT reside in MM at the same time how are we going to address both ??

I need 25 bits to address PT but if I use 25 bits "I MAY END UP USING SOME PORTION OF THE PAGE OFFSET OF ACTUAL PAGE IN MM AS IT IS LARGER IN SIZE THAN PT AND HENCE 1 BIT OF IT ,MSB(13 th BIT) WILL BE USED For referring a page despite it contained data !!"

If you say this does not happen this way, how would I refer PT as well as actual page at the same time.
Please explain this in particular.

Thanks for your  valuable time and help .

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@Gate Keeda: what I think is virtual memory page size is fixed according to fame size in main memory. Since 24 bits are needed to address fame in main memory, we ,AT EACH LEVEL need 24 bits in the PTE to address each frame(And please clear I am NOT saying that page table entry will be of 24 bits, I am saying in each entry of any page table we use 24 bits to refer a frame in MM because after all we are referring a frame out of 2^24 frames).

Now coming to the bits used for indexing. If just 9 bits are used for indexing why would that alter the page size ?? Page size must remain fixed rather we can assume that to make a fixed page size we can increase the PTE size in the page table.(NOTE that still 24 bits will be used to refer a frame but remaining bits that this PTE uses in excess can be used for other purposes or may be not used for anything).

In reference to above question bit 21-29 are used to index second level PT (which is frankly saying a SINGLE PAGE as you said above). Now to make this equal to one page so that it fits in memory frame we must use PTE of size equal to 4KB/2^9=8 Bytes. But this does not mean that we need at, this level 25 bits to address next level PT.We still need 24 bits to refer next level PT but I have used a larger entry size which may contain extra information,no matter what , and this excess information may change at each level of PTs causing different PTE size BUT SAME NUMBER OF FRAME BITS.

This is easy to assume ,that from a page table entry (even if it is of varying size at different levels, we can always pick first 24 bits to address frame/PT (which is stored in frame actually) at the next level).

Respond to this @Gate Keeda

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@Gate-Keeda No. There can be multiple inner level page tables. And that is why multi-level paging is used. Of the numerous possible inner level page tables, only the needed ones will be loaded to main memory.

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@Gatekeeda: I dint say there is only one table. I said when we talk of indexing of a page table we talk about just one page out of many pages at that level.because only one of them will be used for a particular page reference at a time.

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@Sandeep Supporting multi-size pages is not an uncommon thing even for actual page frames (see below link). So, using a different page size for a page table is even simpler. All that is needed is for the MMU to know which page size is needed for the current request and correspondingly fetch that much data from memory. 

http://www-01.ibm.com/support/knowledgecenter/ssw_aix_71/com.ibm.aix.performance/multiple_page_size_support.htm

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there will be multiple inner level page tables. Agree. that's what makes it multilevel paging. But my doubt is.. The logical address is generated for a particular process at a time.. So the number of page tables will be fixed for that particular process...i.e. there is only one page table at third level So, how come we have 2²⁵ number of third level page tables?? 

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No. There can be multiple third level page tables for a process. Usually 2 or 3. 2²⁵ is the maximum such tables possible. 

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Wonderful question for clearing all misconceptions and doubts in Multilevel Paging. And brilliantly answered by Arjun Suresh. In many books answer is given as option (b).

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Good job Arjun Sir!!   Thank you!!

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@Arjun Suresh: Sir I solved the questions given in the link. But following are few doubts :-

1. What is meant by page-aligned in the Problem 3 part 2 solution ?

2. In Problem 3 part 3 solution it is given " First, the stack, data and code segments are at addresses that require having 3 page table entries active in the first level page table, so we have 3 second-level page tables."  

   Now the question is just by looking at three different addresses like given for data, code and stack segment in the question, can we say we have 3 entries in 1st-level Page Table. Or is there something related to grouping of addresses like base address and offset i.e data and code segment come under same group of addresses and stack in other group of addresses so we can say we have two entries. Hope u understood what i want to say?

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can anyone please explain the diagrammatic explanation of this question. ASAP

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awesome explaination sir.

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Diagram for this answer will be

 

related video

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@arjun sir,here i am not understanding one thing,why are we calculating number of tables in each level and why are we considering physical address space for that and even if number of tables are to be calculated then number of entries in first level page table is 2^2 i.e 4,number of tables in second level should be 4 because each entry of first level will point to a page table in next level,hence number of tables at second level should be 4 with 2^9 entries in each table as  9 bits are there in virtual address space to refer to the second level.then number of tables in third level should be 2^11 similarly with 9 bits in each entry of third level page table.

i am very confused..please have a look at it.

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"So, in the given question, a main memory page frame is fetched with 24 bits of address and 12 offset bits, while the page frame corresponding to a third level page will be fetched using 25 bits of address and 11 offset bits (9 bits from VA + 2 bits for 4 bytes of PTE)."

So is my following conclusion correct(and consequently the understanding of the concept)?

1) There are 2^25 3rd level page tables.

2)There are still 2^9 entries in each 3rd level page table,but each page entry has 4 bytes,so offset(the size) becomes 2^11, and 4 bytes is 32 bits, we are using only 24 bits out of 32 for addressing page frames?

3)There are 2^25 2nd level page tables,There are still 2^9 entries in each 2nd level page table, PTE size is 4 bytes, so 32 bits are present but we are using only 25 bits out of 32 bits to address the 3rd level page tables(because we found out that there are 2^25 3rd level page tables)?

4)There are (2^36/((2^2)*(2^2)))= 2^32 1st level page table,each table has only 4 entries, but each page table entry contains 25 bits to address 2nd level page table?

5) So in layman terms, before we were going from left to right to calculate and splitting up the page tables for virtual address calculation, now we are doing up the reverse, for accommodating the page framesthe no of page tables do not remain the same at various levels,only thing remaining constant is the no of entries of page tables at each level and the PTE size, so we can calculate the offset bit for calculating the no of page tables possible?

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https://gateoverflow.in/61310/question-related-to-gate-2008_67-complex-question

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@arjun sir,  After reading the solution all my enitre concept in Paging is thrashed :(
I didn't understand many things .

Question1
First of all , What is the question really asked ?

"The number of bits required for addressing the next level page table(or page frame) in the page table entry of the first, second and third level page tables are respectively "

Does this mean.. In 1st 2nd and 3rd page table entries how many bits are used as frame number ?

Question 2
I didnt understand this equation .
Number of third level page tables possible= $\frac{Physical memory size }{Size of a third level page table}$

How it is possible to get # 3rd LEVEL page tables by Dividing entire physical memory with Size of 3rd level page  table . Doesn;t the physical memory include both 1 , 2 , 3 level page tables and pages .

Question3
According to What I knew , Number of entries in outer page table is the number of inner page tables .
In light to this we must calculate from outer most page table to inner for finding number of page talbes BUt you provide a topic turvic solutions to my conceptual understanding.  I didn't get this part . Why did u calculate it like that .

Moreover do the last level contains many page tables ? What I knew is the page number from last  page table will gives the fram number to get a PAGE not another PAGETABLE
But you provided a equation like that " Number of third level page tables poosible " 

Could u pls help me ? Im getting totally confused !!

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Question 1: yes. But "frame number" are used for page frames (not for page tables) and hence they did not use the word. See this part

next level page table(or page frame)

Question 2: Yes, here we are going for an upper bound (the leasr possible upper bound).

Question 3:

Number of entries in outer page table is the number of inner page tables

This is true only for 1 level paging or for the first page table. Since there is only one page table, each second level page table (or page frame) requires a distinct entry in first level page table. So, in the given question we have 2 entries in first level page table and hence there must be just 2 second level page tables possible. But I wrote $2^{25}$ which is meant to denote the no. of possible addresses of second level page tables (this needs change). Had the second level page tables been at fixed location - possible in a uniprocessor system - we would have needed just 2 bits for addressing the second level page tables here. 

Moreover do the last level contains many page tables ? What I knew is the page number from last  page table will gives the fram number to get a PAGE not another PAGETABLE
But you provided a equation like that " Number of third level page tables poosible

The question is for 3 level paging. So, there are many page tables in 3rd level. From the third level page table, we get a page number which points to a page. I guess you got confused with the level here.

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This is wondrfully explained . Thank you so much @arjun sir :)
Just one more point to get clarified ,

Number of third level page tables possible= $\frac{Physical memory size}{Size of a third level pagetable}$

I didn't understand why are u using this equations  beause physical memory will contain all pages tables not just the entries of 3rd level .

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@Arjun sir:

Isn't it that each inner level page table is itself paged and the frame no of each of these inner pages is stored in outer page table?

So do you mean "number of pages of 3rd level page table" by "number of third level page tables possible" ?

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@pC yes, that will be more accurate. But more complex to calculate and here we are doing an upper bound only.

@Pratyush Yes, we are doing paging of page tables- but by standard notation it is not correct to refer to them as "pages" as they are page tables.

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@Arjun Sir,

In third level we have 2^9 enteries and we need to point to 2^24 frames of main memory,so we should have 2^24/2^9 page tables for thirs levels?Why are we takng entire RAM ,we need to how many frames are there and not the entire address space.please help

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@Arjun Sir
A BIG thanks to you for the explanation.
"we should not assume that page tables are page aligned."  This line added a special charm to the solution.
Once Again, Amazingly explanaied. Cleared many myths that all coaching teach.

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@pc, why you think that is not correct ?

You must have missed something from that explanation.

I am trying to explain the crux, See if this makes sense to you-

Key Point: We can divide anything (process, any level page Table) to any size, and accordingly we have to divide MM.

When we divide Process to some size, then that size is called page/frame, we divide MM into frames.

When we divide page table to some size ($2^k$), then that size has no special name (like above frame). we also divide MM into size of $2^k$.

2

9

9

12

Outermost page table need to address one of the 2nd level page table, Question is how many bits it will take?

Before answering this a simple questions:

 you have $2^{36}$ bytes of memory, you need to address one byte, how many bits you need?

- 36 bits  (Because there are $2^{36}$ Bytes)

you have $2^{36}$ bytes of memory, you need to address one 2KB block, how many bits you need?

- 25  bits  (because there will be such $\frac{2^{36}}{2^{11}}= 2^{25}$ blocks. )

This says: if you want to address some block or chunk, then number of bits depends on,  howmany such blocks are there.

If we organize (divide) MM into size of each block, then howmany such blocks will be there.

Each 2nd level page table size = $2^9 \times 2^2 = 2^{11}$

Now , Outermost page table wants to address one of the 2nd level page table.

 If we partition MM into each of size $2^{11}$ then there will be $\frac{2^{36}}{2^{11}}= 2^{25}$ partitions.

And 2^nd level page table can fit into one of such partition.

Therefore Outermost page table wants 25 bits to address 2nd level page table.

Important thing to notice here is MM is divided into chuncks of $2^{11}$ wrt page table, and at the same time MM is divided into frames (of size $2^{12}$).

Now say if address split is this:

3

8

9

12

outermost page table size = $2^3 \times 2^2 = 2^5$

2nd level page table size = $2^8 \times 2^2 = 2^{10}$

innermost level page table size = $2^9 \times 2^2 = 2^{11}$

Now wrt to :

1.outermost page table:

MM is divide into chunks of $ 2^5$, therefore to address outermost pagetable we need ( $\frac{2^{36}}{2^5}= 2^{31}$ ) 31 bits in Page Table Base Register.

2. 2nd level page table:

MM is divide into chunks of $ 2^{10}$, therefore to address 2nd level page table we need ( $\frac{2^{36}}{2^{10}}= 2^{26}$ ) 26 bits in outermost page table entry.

3. innermost level page table:

MM is divide into chunks of $ 2^{11}$, therefore to address innermost pagetable we need ( $\frac{2^{36}}{2^{11}}= 2^{25}$ ) 25 bits in 2^nd levelpage table entry.

4.Process:

MM is divide into chunks of $ 2^{12}$, therefore to address actual page we need ( $\frac{2^{36}}{2^{12}}= 2^{24}$ ) 24 bits in inner most levelpage table entry.

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thank you sachin ... for more simplicity of concept :)

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Pleasure :)

Continuing last comment-

It's Just a view of memory that everyone has-

• Cache thinks that MM is divided into lines.

• Process thinks that MM is divided into Frames.

• Secondary memory thinks that MM is divided into Blocks.

• Page tables thinks that MM is divided into chunks of size $2^k$, here $2^k$ is size in which we divide Page table itself.(Again saying, Page tables need not to be page aligned, we can divide page tables into any size and accordingly we divide MM into same size so that each partition of Page Table can go and fit into one of the partition of MM. Again, That partition size could be anything, need not to be same as page size. Actually that partition size has nothing to do with page size.)

Now one may wonder that if we can divide PT into any size, then why to divide at all this is same as saying "Why to have multi level paging?"

Answer of this question is in this video

Here it is beautifully explained the need of multilevel paging and how this helps to reduce page table size. See this question here, this is an example of how using multi level paging we can drastically decrease page table size.

I recommend all set of videos of VM.

Once you done with all videos (total length is 1 hour) then these kinds of questions will make more sense to you - GATE-09 Question.

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Can someone please explain why we are doing Physical memory size$ /$Size of a third level page table to calcualte number of third level page tables?
Shouldn't the page table contain the entries which are indexed based on virtual address and mapped to physical address? And so shouldn't it be Virtual memory size $/$Size of a third level page table ?

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No. See page tables are also stored in "physical memory". Hence we are finding the no. of possible addresses for it. Virtual memory is directly relevant only for first level page table.

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If I understand it correctly, we are using the virtual address as follow
bit 30-31 - to find the entry in first level page table which points to second level page table.
Next 9 bits are used to find the entry in second level page table, which points to third level page table.
Next 9 bits are used to find the entry in third level pable table, which points to actual physical page.
And last 12 bits are used as offset in this physical page.

So in total the number of entries in third level page table that will be pointing to physical pages is $2^{2}*2^{9}*2^{9}=2^{20}$ . Each of these third page table entries is 4 byte i.e. 32 bits, so in total  $2^{20}*2^{5}=2^{25}$ , therefore third level page table will need 25 bits.

Where do you think I am going wrong?

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@Arjun I see what you are saying now. Thanks! I guess this problem is difficult only because of the text.

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@sachin..please check these 

1. The pointer (p) stored in an entry of the outer (1st) level page table will point to an inner (next 2nd) level page table starting address.
2. If inner level page tables are stored in a page/frame aligned organization then p needs to index the possible frames in MM, So, p size = frame no size.
3. If inner level page tables are NOT stored in a page/frame aligned organization.
   1. Assuming inner page tables are stored in MM in a contiguous manner in size of one such 2nd level page table.
   2. Then p size = $\begin{align*} \log_2 \left ( \frac{\text{MM size}}{\text{one 2nd level PT size}} \right ) \end{align*}$
4. In this NON-page/frame aligned organization, the bits required to search (or locate) one-page table in MM depends upon the size of that page table itself. And these bits may be stored in different places (base register, page entry etc) depending which page table we are looking for.

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If any of above lines is incorrect, then please mention that. Moreover,

Could you please provide some links or source that indicate then NON-page/frame alignment of PT storage or possible real implementation. Because I have searched a few that says, page-alignment structure only. 

(note that if you have such source already, then ok ! other wise no need to search too much)

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To me ur every point seems to be fine.
U can solve questions here- http://www.cs.utexas.edu/~lorenzo/corsi/cs372/06F/hw/3sol.html

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Sir,

Only one thing to ask these 24, 25 and 25 bits are part of page Table entry size (Here 4B = 32 bits). Right??

And pte include other aadditional info. like valid bit etc..But never uses the number of bits to adress next level page table beyond the page table entry size. Right?

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@Debashish @Sachin

https://gateoverflow.in/61310/question-related-to-gate-2008_67-complex-question

in 3 or 4 level page table if only 1st level contains offset of the page, why other level not contains the offset?

if the 2nd and 3rd level page table size $2^{25}$ bytes and number of PTE only $2^{9}$ and page table entry size is $2^{2}$ Bytes , then is $\left (2 ^{25}-2^{9} \times2^{2}\right )$ could be used or it totally wasted?

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@Sonam

Acc. to Sachin's solution

if

outermost page table size = $2^3 \times 2^2 = 2^5$

2nd level page table size = $2^8 \times 2^2 = 2^{10}$

innermost level page table size = $2^9 \times 2^2 = 2^{11}$

then size of physical memory will be 5+10+11+12=38

But in given question physical memory size is 36 B

Isnot it?

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i think ,you misinterpreted , he gave another example

"Now say if address split is this:" i think

@sachin ek bar dekh

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I am not sure If I got above conversation.
Just making one point that I have taken separate example to clarify more.

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@Sachin

https://gateoverflow.in/61310/question-related-to-gate-2008_67-complex-question

chk my command here

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@Arjun sir

wow!! what an explanation !!! Great work...

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Why are we dividing number of physical pages possible (2^36) by size of an entry (PTE)?

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Thanks, @arjun sir for the great answer!

Thanks, @sachin for giving such a great explanation. I actually understood this concept after seeing your explanation. It would be great if you could add it as an answer.

Thank God! I saw this question on this site before completing virtual memory concept. Actually, still many teachers are teaching it the wrong way. Also, Tanenbaum hasn't covered this part in detail which sends everyone in believing that like the innermost table, every other level page table considers page size as the only distribution of memory.

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One more thing I need to know @Arjun Sir

In ur ans u told

" number of possible third level page tables  u have to calculate from bits from 12-20 index number"

for " number of possible second level page tables u have to calculate bits from 21 to 29 index number"

then for 1st level page tables why u not calculated from index number 30-31?

I mean why it direct taken from number of bits in page frame?

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sir , i would like to ask one thing suppose if u r asked size of frame required to store process then u will devide frames as size of 2^36/2^12 =2^24 , but to store page table frame size should be 2^36/2^11=2^25 , as we know that main mem will be devided in equal frame then which size we will prefer ?

if u will devide frame with 2^25 then then to store 2^24 will leads lots of internal fragmentation

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@saket nandan

I think you need to read Sachin sir's comment above ! Things are crystal clear in that :)

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@Arjun sir

// only third level page table entry points to data frames//

now, total page tables at third level = 2²⁵ 

each third level page tables contain entries = 2⁹

each entry corresponds to 4KB(2¹² bytes) data frame.

according to this total virtual address = 2²⁵*2⁹*2¹²= 2⁴⁶ bytes, or 46 bits virtual address, but in qsn virtual address is limited to 32 bits.

so how could this be possible?

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@saket Who told tht main memory can only be divided equally between pag frames and page tables? Who divides it?

@Joshi As told in the answer, there is no requirement that a given process addresses all available physical memory space. But a physical address must be large enough so that every possible address can be used (by some process).

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joshi_nitish  

at third level no. of page table would be...2¹¹.

Virtual address space is...2 9 9 12    ..now here...

1st level:- 1 page table, 2² entry and each entry cotains single...next level page table..

2nd level:- 2² page table and each containing containg 2⁹ entry.. .and each entry having next level page table:

3rd level:- 2² * 2⁹ page table and each having 2⁹ entry...at third level total no. of entry would be 2²⁰.which is equal to the no. of pages in the process(i.e 2^32-12)...i.e virtual memory devided by page size...

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@hs_yadav

see, Arjun sir's answer..

no. of page tables possible at 3rd level is 2²⁵

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@joshi_nitish

yes at third level we can have at max 2²⁵ tables but out of these how many will be actually used depends on the memory requirements of a process.

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@sachine ....i thinnk paging is applied on process so we need to split logical address then why  dividing physical address??

clear the doubt

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@Arjun sir,

If at level $i$ we have $2^x$ page tables,then at level $i-1$ we will have $2^x$ entries and each entry will have $x$ bits in its PTE to address next level page table.(Although PTE can have other information also along with $x$ bits)

Please verify

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I have a little doubt over calculation as physical address is given in bits (36 bits) and frame size is given in Bytes (4KBytes) . the calculation done is 36-12 = 24 ,so how you took 12 here ? because it should be 2¹⁵ rather 2¹² .I'm sorry but I'm not getting this calculation .please clarify ,thank you!

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We address a byte and sometimes multiple bytes which is termed a word. There is usually no "bit addressing".

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Obviously I'm getting that its byte addressing but my question is specifically about calculations done ,to be more specific I don't get how can bit and byte both involved in single calculation without interchanging one to other .How can byte be subtracted from bits ,wouldn't it lead to wrong calculation ? going at binary level we need bits . few bits becomes bytes and few of those bytes becomes a frame or block or whatever but the ground level is bits only ,isn't ? I see it as you have set of bits for addressing like MM or VM ,in power of 2 for calculative simplicity and then we divide it in index offset etc etc and then address translation through mapping it further where we set few bits (a collection in terms of byte or word) to define frame and it goes like that ,right ? but the binary ground is bit only. I hope you I'm capable of explaining my confusion ..please clarify .thank you!

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@Arjun sir

Correct me if I'm wrong, this is what I understood from your solution to this question:

First level page table has 2 bits, so it can point to 4 second level page tables, and each of its entry is of 25 bits.
Second level page tables has 9 bits, so each second level page table can point to 512 third level page tables, and each of its entry is of 25 bits too.
Third level page tables has 9 bits to it, so each third level page table can point to 512 main memory frames, and each of its entry is of 24 bits.

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what a nice explanation @ Arjun sir

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@Arjun Sir 

I am getting doubt with meaning of these line in answer

firstly "A page in logical address space corresponds to a page frame in physical address space. "

shouldnot this line be "A page size  in logical address space corresponds to a page frame size in physical address space." 

because the offset part of logical address and physical address is same, but number of frame and number of pages of both addresses are not same

Plz elaborate this line

Secondly " there is only 1 first level page table. But there can be many second level and third level page tables "

how to know first level that means at end level there shouldnot be more than 1 page table?

 

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did you get answer for ur que @eyeamgj

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YES daksirp 

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can you explain me,

generally we divide physical address,

but here virtual address space is already divided into page tables.

and i tried to understand answer given by @Arjun sir, in his answer

he is dividing whole physical address space by size of Nth level page table, this means only Nth page tables are ftaking whole space of Physical address space, what about N+1, N+2 level page tables, where they will fit if Nth level page table is taking the whole space.

Actually im not get this concept. xplain it ??

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Same doubts as srestha.
Why we are dividing VAS in to pages when it can easily fit in PAS ? As size of physical address is more than virtual address so why do we need to implement paging in this case!!

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any1 answer this please ??? or atleast xplain what we did in answer of @Arjun sir

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Thanks Arjun Sir for the wonderful explanation

Thanks Sachin Mittal 1 for the Brilliant Explanation and breaking the concepts in pieces. Understanding this is not very difficult but it's also not very easy.

By mistake i clicked on flag button for spam on your comment . Sorry about that. :)

I think 1 video for this particular concept is required as this concept is not discussed anywhere

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If there happen to be only 2²⁴   frames in physical address space then how can we need more than 24 bits to address this memory?? Confused any help would be welcomed

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Thank you so much for such great insights. Really helpful. :)

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@Arjun sir ,

Just a small doubt ,As we found that number of bits required to address next level page table are 26,25,24

But the size of PTE at each level is 4B..how the entry is maintained 4B at each level ..because rest of options like valid dirty will take same space in each entry.

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4 bytes doesn't mean all bits are in use. When we use 25 bits for address we still have 7 extra bits for page protection and replacement policies.

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Got it sir,,thanks

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• Arjun Sir,
• I cant seem to figure it out, Please help me on this.
• If there happen to be only 2^24   frames in physical address space then how can we need more than 24 bits to address this memory? I understood ur explanation that page table entries maybe of variable sizes but how does it all actually plays out?

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@Sachin Mittal 1 If Process thinks that MM is divided into Frames and insert data in some frames out of 2^24 and Page tables thinks that MM is divided into chunks of size 2^k and insert page tables some out of 2^25 chunks, won't there be a possibility of processes and page tables overlapping?

Please clarify.

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@Arjun @Sachin Mittal 1 @Debashish Deka @srestha (sirs) if we page the physical address space then how does the mapping from virtual to physical address takes place?Is virtual address space is also paged ?but why do we need to page the physical address space when processes can work only 4 GB VAS?

 

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@Arjun Sir, @Sachin Mittal 1 Sir, please reply, 25+25+24=74 right? but Physical address space is not 2^74 right?

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@Arjun

Hello,  I do not quite follow the explanation you have given. According to my understanding , each page table has to be stored in the main memory (irrespective of levels ,also TLB is not assumed here). From the virtual address, we could select the index of the page table(s) , and corresponding index values always contains a frame address (because the page table/page pointed by that particular index has to be stored in main memory). So ,since the PAS is 24 bits ,we only need in 24 all page level entries to address the next level page table. I thought about this a lot and cannot find any flaw in my reasoning.

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@Arjun-Awesome Answer and Awesome Assignment questions.They really now made me good in multi-level paging concepts.Thank you sir. :)

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I understood the answer sir.... but in general...we r given 12 bits for offset and 20 bits for page table entries..so how can we get 25 bits for addressing pages..the virtual address is only 32 bit.....

In general we  load the required page table to physical memory when needed....so with 2^9 page table size in third level we r accessing 2^24 frames means we have 2^15 page tables in third level and we load required page table when needed.so only 9 bits are sufficient.....

I think in question it is asked in general which is not possible.......am i correct sir..........

If 25 bits are required in all levels we can go for single level paging..

Sir if we gone for single level for this question we have only 20 bits for page table and we require 24 bits for addressing the frames.....is it okk not to have all frame addresses in page table.....?????....

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@Arjun sir, @Sachin Mittal 1 

I have a doubt here..

3 rd level page table is of size $2^{11}$ Bytes. So with respect to 3rd level page table, main memory is partitioned into blocks of size  $2^{11}$ Bytes and a 3rd level page table sits into one such block.

So there must be a base address to that block right? My question is how do we get that base address of block(36 bits) in which 3rd level page table sits..

 we just get the block number(25 bits) from the 2nd level page table and 9 bits from the address to index into the block(i.e. the 3rd level page table) .

where am i going wrong??

http://www.cs.utexas.edu/~lorenzo/corsi/cs372/06F/hw/3sol.html

In the 2nd sub problem of 3rd problem, they don't have this issue because they have taken entire physical address in each page table entry...

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How can the number of page tables possible in a process depend on the size of physical memory?

I think there are 2^24 frames possible so number of bits required to address those frames would be same i.e 24 in all levels.

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As there will be 4 entries in first level page table. So at max it can address 4 second level page tables. But we have almost 2^25 second level page tables. So my question is how first level page table will address these many tables?

As the process might not use all the page tables. So, will at a time maximum 4 second level page tables be addressed which are being used by the process, by referring their respective addresses from first level page table. 

Please tell me the addressing way of these huge amount of tables. @Arjun sir.

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@Arjun i understood that page table size need not be aligned with the actual page size, but that implies that a page table needs to be distributed among different frames, because it can be a few pages long.

In that case, say for example a second level page table has 2^12 entries, and each entry is 32 bits (4bytes) long, therefore page table size is 8KB, and my frame size (page size) is 4KB, that means the second level page table would be stored in 2 pages, and therefore 2 frames in the physical memory. Now, in the first level page table, there would be only one entry per 2nd level page table, and it would point to only one of the 2 frames in which the page table is stored. 

How would this work? Am i thinking in the wrong direction by assuming that page tables (even though they need not fit in a single frame) are divided into pages and placed in random available frames?

Also, in the homework questions link you provided, they mention

“The top-level page table should not assume that 2nd level page tables are page-aligned. So, we store full physical addresses there”

But in this case you are only considering 25 bits to address a 3rd level page table from a 2nd level page table. Please help. let me know where im going wrong! 

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relly thanx man you saved me from maze of pagging

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amazing explanation sachin sir :)

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@Arjun sir, @Sachin Mittal 1 sir, thanks a lot for the great explanation! My understanding of multi level paging and virtual memory was so wrong until now. Thank you!

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http://www.cs.utexas.edu/~lorenzo/corsi/cs372/06F/hw/3sol.html 

 This source shared by @Arjun sir, is extremely useful.

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@Arjun @Sachin Mittal 1

in the provided questions of CS372 in 3^rd question 2^nd part it is saying that 2^nd level and 1^st level page table will address to whole physical memory hence at least the bits per entry will be same as bits of physical memory . i am not able to understand this?

BUT

as per the explanation bits per entry of any level depends on what it is pointing to , i mean as inner most level is pointing to pages or frames so MM is divided into pages and hence the bits per entry of innermost is calculated.

similarly for ith level entry (bits) is decided on how i+1 ^th level single page table is dividing MM into chunks.

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@mayajeet Sharing whatever I understood, in case it helps –

That is because in the CS372 question, we are being provided with the process’ physical memory requirement itself (in the above PYQ, we were provided with just the MM size, in which case we calculate for the worst case scenario - refer towards the end of Arjun sir’s video linked in the best answer), and we found out that only a single 3^rd level page table suffices for all the pages of the process. Now, this 3^rd level page table can actually be placed anywhere on the physical memory (had we not known beforehand how many 3^rd level page tables are required, then we need to divide the MM into chunks of 3^rd level page table size for maximum physical memory usage). Moreover, the answer of the CS372 question further explains how aiming for a low sized chunk division of the MM is not feasible (PTE size grows larger than 4B), and how increasing the size of this chunk saves us no more space than just storing a regular pointer in the PTEs of the first and second level page tables, and just using the regular memory allocator.

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can you please provide the links for the set of VM videos again?

Answer 2

Answer by Arjun Sir and Sachin Sir are really great :)

I am just trying what I understood and hope it will be helpful for aspirants like me.

 

Comments

OK,YOU HAVE SAY THAT WE NEED 2^25 TABLE AT LEVEL 3 AND THAT'S WHY WE NEED 25 BIT IN SECOND LEVEL FOR ADDRESSING 3rd LEVEL PAGE TABLE.NOW SEE THIS

AT SECOND LEVEL WE STORE 2^25 ENTRIES AND PAGE TABLE SIZE AT SECOND LEVEL IS (2^9)*4=2^11 byte.SO NUMBER OF TABLE WE GET AT LEVEL 2nd IS (2^25)/(2^11) =2^14.

SO AT LEVEL 1st WE MUST HAVE 14 BIT TO ADDRESS TABLES OF 2nd LEVEL

CORRECT ME IF I AM WRONG

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SECOND THING IS THAT IF YOU CONSIDER THAT WE HAVE TO  PERFORM (2^36)/(2^11) TO OBTAIN NUMBER OF PAGE TABLE AT LEVEL 2nd THEN MY QUESTION IS WHY??

AS WE KNOW THAT IN MULTILEVEL PAGING CONCEPT WE HAVE TO FIND THE PAGE TABLE ADDRESS OF NEXT LEVEL AND FROM THAT NEXT LEVEL PAGE TABLE WE HAVE TO FIND THE ADDRESS OF NEXT LEVEL PAGE TABLE ,AND THIS PROCESS CONTINUE DEPENDING ON LEVEL OF PAGING.

SO IN 4 LEVEL PAGING IF WE CONSIDER LAST PAGE TABLE THEN IT MUST CONTAIN ADDRESS OF PAGE TABLES OF 3rd POSITION.IT IS NEVER GOING TO CONTAIN ADDRESS OF WHOLE PHYSICAL ADDRESS SPACE.IAND IF IT GOING TO CONTAIN ADDRESS OF DIRECTLY PHYSICAL ADDRESS SPACE THEN WHY WE APPLY MULTILEVAL PAGING,JUST ONE PAGE IS ENOUGH.

CORRECT ME IF I AM WRONG

Answer 3

Total no. of physical frames = 2^(36)/2^(12) = 2^24  
Therefore, bits needed to address a physical frame = 24 .
Now, A 3rd level PTE[Page table entry] contains  "bits to address a Physical frame"[final mapping from virtual to physical address] + valid/Invalid bit + some other bits[R/w etc.] .

But, question specifically asks for only "bits needed to address the next level page table or page frame".
So, the bits needed to address the page frame is 24.      

A 2nd level PTE[Page table entry] contains  "bits to address a Physical frame"[Physical address where a 3rd level page resides in main memory ] + valid/Invalid bit + some other bits[R/w etc.] 
So, the bits needed to address the page frame/next page table is 24. 
Similarly,
A 1st level PTE[Page table entry] contains  "bits to address a Physical frame"[Physical address where a 2nd level page resides in main memory ] + valid/Invalid bit + some other bits[R/w etc.] 
The bits needed to address the page frame/next page table is 24. 

Hence , the answer is B .

See figure 2 here for reference : http://www.cs.berkeley.edu/~kamil/teaching/sp04/031104.pdf  .
 

Comments

So, does that mean the page tables are not present in frames?

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"Page tables in frames" means?

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https://www.cs.utexas.edu/~lorenzo/corsi/cs372/06F/hw/3sol.html 

Here, in problem 2:

In solution, point number 2 should be: With 4-byte entries in the page table we can reference 2^34 pages. Since each page is 2^13 B long, the maximum addressable physical memory size is 2^34 * 2^13 = 2^47 B (assuming no protection bits are used). 

REASON: 2^36/ 2^2 = 2^34, please correct me if I am wrong.

Answer 4

TO ALL THE CONFUSED GUYS LIKE ME I WILL MAKE EVERY THING CLEAR;;

WHATEVER WE HAVE LEARNT IS 100% CORRECT..... SO BE HAPPY   SEE HOW

1-- THIS QUESTION DUE TO THE USE OF JUST ONE WORD IS MAKING EVERYTHING CONFUSING AND WE ARE NOT SEEING THAT WORD.  

IF QUESTION WOULD HAD BEEN 

A processor uses 36 bit physical address and 32 bit virtual addresses, with a page frame size of 44 Kbytes. Each page table entry is of size 44 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows:

• Bits 30−31 are used to index into the first level page table.
• Bits 21−29 are used to index into the 2nd level page table.
• Bits 12−20 are used to index into the 3rd level page table.
• Bits 0−11 are used as offset within the page.

The number of bits required for addressing the next level (SEE THE DIFFERENCE HERE HERE WE REMOVED THE WORD PAGE TABLE) page frame in the page table entry of the first, second and third level page tables are respectively.

SO THIS IS WHAT WE HAVE LEARNT EVERYWHERE . HERE EVERYTHING WILL BE DIVIDED INTO FRAMES WHICH IS SAME IS PAGE SIZE. AND THUS NOW EVEN IN CASE OF MULTILEVEL PAGING IF THE PAGE TABLE OF INNER PAGE TABLES ARE DIVIDED INTO PAGES OR FRAMES (SINCE PAGE SIZE=FRAME SIZE) THEN THEN FOR FINDING THE NEXT LEVEL PAGE FRAME IN THE PTE WE JUST NEED THE NO OF BITS REQUIRED TO REPRESENT FRAMES WHICH IS 24.

HENCE ANSWER WOULD HAD BEEN 24,24,24

 

BUT THEY HAVE CLEARLY GIVEN 

The number of bits required for addressing the next level page table (or page frame)  in the page table entry of the first, second and third level page tables are respectively.

IT CLEARLY MEANS THAT SINCE 3RD LEVEL WILL BE POINTING TO THE ACTUAL FRAMES WHERE THE PAGES OF THE PROCESS ARE PRESENT IN THE MM HENCE THEY COULD BE PRESENT ANYWHERE IN THE MM FRAMES AND WE HAVE 2^24 FRAMES HENCE WE NEED 24 BITS FOR SURE AT 3RD LEVEL PAGE TABLE .

SO  EITHER B OR D COULD BE POSSIBLE 

a)    NOW 2ND LEVEL PAGE TABLE WILL BE POINTING TO THE 3RD LEVEL PAGE TABLE NOW SINCE IN THE QUESTION IT IS EXPLICITLY AND DELIBERATELY GIVEN THAT ADRESSING THE NEXT LEVEL PT OR PAGE FRAME HENCE HERE THEY MEAN PAGE TABLE NOT PAGE FRAME.

b)  ACTUALLY HERE IF WE DONT CONSIDER THE BITS DIVISION GIVEN BY THE QUESTION SETTER THEN WE NEED JUST 2 LEVELS OF PAGING UTILIZING VERY EFFICIENTLY BUT SINCE THEY HAVE NOT UTILIZED IT 100% HENCE THATS WHY WE HAVE TO THINK DIFFERENTLY .

c) AT LEVEL 1 WE HAVE 2 BITS IT MEANS WE HAVE 4 ENTRIES HERE SIMPLE. AND HENCE LEVEL 1 SIZE WILL BE 4*SIZE OF EACH ENTRY = 4*4B=16B

AT LEVEL 2 WE HAVE 9 BITS IT MEANS USING PAGE TABLE BASE AND LEVEL 1 IF WE GO TO A PARTICULAR FRAME IN LEVEL 2 THEN HERE ENTRIES PER PAGE/FRAME = 2^9  AND HENCE LEVEL 2  EACH PAGE/FRAME    SIZE WILL BE 2^9 *SIZE OF EACH ENTRY = 2^9*4B=2*11B

SEE WE HAVE PAGE SIZE =2^12 B BUT WE ARE USING JUST 2^11 IT MEANS WE ARE USING JUST THE HALF SIZE OF THE PAGE 

AT LEVEL 3 WE HAVE 9 BITS IT MEANS USING PAGE TABLE BASE AND LEVEL 1 AND LEVEL 2 WE WENT TO EXACT FRAME IN LEVEL 3 THEN HERE ENTRIES PER PAGE/FRAME = 2^9.    AND HENCE LEVEL 3 EACH PAGE/FRAME SIZE WILL BE 2^9 *SIZE OF EACH ENTRY = 2^9*4B=2*11B

SEE WE HAVE PAGE SIZE =2^12 B BUT WE ARE USING JUST 2^11 IT MEANS WE ARE USING JUST THE HALF SIZE OF THE PAGE .

THATS WHY WE HAVE TO GO A/T THE QUESTION WHICH CLEARLY MEANS THAT PAGE TABLES ARE NOT DIVIDED INTO PAGES RATHER THEY HAVE BEEN DIVIDED INTO SOME CHUNKS OF SOME OTHER SIZE (NOT PAGE SIZE) SO HERE

DELIBERATELY I WILL USE THE TERM NO OF BITS REQUIRED FOR ADDRESSING NEXT LEVEL PAGE TABLE (NOT PAGE FRAME)  ..

SO NOW A/T LEVEL 2            LEVEL 3 HAS BEEN DIVIDED INTO EACH CHUNK SIZE IS 2*11B (EARLIER WHAT I HAVE MENTIONED AS SIZE OF EACH PAGE/FRAME).

SO FOR LEVEL 2 IT HAS TO LOOK INTO THE MM/ PHYSICAL MEMORY WHERE LEVEL 3  CHUNK WILL BE PRESENT AND THERE ARE CHUNKS OF SIZES 2*11B AT LEVEL 3 .... SO LETS CALCULATE HOW MANY SUCH CHUNKS ARE THERE = SIZE OF PHSICAL MEMORY / SIZE OF EACH CHUNK = 2^36/2^11= 2^25 

THUS AT LEVEL 2 TO GO TO A PARTICULAR CHUNK OF LEVEL 3 WE NEED 25 BITS

d)   NOT AT LEVEL 1 WE HAVE TO GO TO A PARTICULAR CHUNK IN LEVEL 2 SO LEVEL 2'S EACH CHUNK SIZE = 2^11B(EARLIER WHAT I HAVE MENTIONED AS SIZE OF EACH PAGE/FRAME).

SO FOR LEVEL 1 IT HAS TO LOOK INTO THE MM/ PHYSICAL MEMORY WHERE LEVEL 2  CHUNK WILL BE PRESENT AND THERE ARE CHUNKS OF SIZES 2*11B AT LEVEL 2 .... SO LETS CALCULATE HOW MANY SUCH CHUNKS ARE THERE = SIZE OF PHSICAL MEMORY / SIZE OF EACH CHUNK = 2^36/2^11= 2^25 

THUS AT LEVEL 1 TO GO TO A PARTICULAR CHUNK OF LEVEL 2 WE NEED 25 BITS.

HENCE WE NEED 25BITS,25BITS,24BITS.

SO FINALLY WHATEVER WE HAVE LEARNT IS CORRECT . WE HAVE ALWAYS ASSUMED IN OUR LEARNING THAT PAGE SIZE WILL BE 100% UTILIZED BUT IF GATE WANTS TO USE INEFFIECIENCY THEN IT IS THERE FAULT NOT OUR FAULT.  IN THAT CASE SOLVE LIKE THIS.

 

 

 

 

  

 

 

 

Comments

Your answer is more explanatory than arjun sir's. Especially the first half of the frame is chunks.

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Amazing Explanation Sir!

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brilliant