GATE CSE 1987 | Question: 2a

Question

State whether the following statements are TRUE or FALSE

In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.

Comments

What if both requests come during last phase, then which request is served?

Answer 1

i think it should be true ....consider a system in which we have modules like FETCH,DECODE,EXECUTE,WRITE-BACK..

now say both DMA request and interrupt arrive during DECODE cycle.....

CPU always look for DMA after every phase(like fetch,decode)but CPU see interrupt only after end of instruction....

reason is that if we allow interrupt in between the phases...interrupt may change current registers and program status word....so its always done that DMA can be allowed in phases(as it dont changes the register content)...but interrupt not....

Comments

If CPU temperature sensor interrupt occur then what happened bro..

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@Vidyadhar , Did you get the answer to your question bro?

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@jiminpark @VIDYADHAR SHELKE 1

In that case it will  leave everything and saves itself first,

means it will service the interrupt. :)

 

so answer of this question is not entirely correct.

Answer 2

The HOLD input has a higher priority than the INTR or NMI interrupt inputs.

So the answer is true.

Comments

What if the interrupt is due to some sensor and DMA is requesting a bus for printer operation?

Priority of sensor interrupt should be more na.

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what if the interrupt is internal?? at that time the interrupt should be given more priority !

clear this thing please!

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@Divyanshu Shukla Assuming the CPU is in IDLE state and then suddenly there is an interrupt due to some sensor and DMA is requesting a bus for printer operation simultaneously. We have to see whether the HOLD signal is high or low during the CLK=1, if it is high, then the DMA request will be prioritized, and if it is low, then such interrupt(generally non-maskable in modern systems) will be prioritized.

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@VIDYADHAR SHELKE 1, @jiminpark, @Pranavpurkar, If the internal interrupt is maskable(which is a rare scenario in modern systems), then it will not be given more priority w.r.t. DMA request. But if the internal interrupt is non-maskable, which is the general scenario in modern systems, an interrupt like a temperature sensor “may” trap the CPU. And we have to see the strength of the HOLD signal in the next Clock.

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HOLD vs. Interrupts scenario -

In the case of 8085A, it uses the T(hold) state to momentarily cease executing machine cycles, allowing external devices to gain control of the bus and perform DMA cycles.

As regards T(hold) and T(halt), three situations can occur: ( During T(halt) – the CPU stops executing the instructions and is IDLE.)

1- The CPU is in T(halt) state – During CLK=1 of every T(halt) state, the processor internally latches: (a) the state of the HOLD line, (b) Any unmasked interrupts. If the HOLD is high, then on the following CLK=1 CPU exits T(halt) and enters T(hold). This takes place even if a valid interrupt co-occurs with the HOLD signal(which is high).
2- The CPU is in T(hold) state: During CLK=1 of every T(hold) state, the processor internally latches: (a) the state of the HOLD line, (b) Any unmasked interrupts. If the HOLD is low, then on the following CLK=1 CPU exits T(hold) and enters T(halt). If any unmasked interrupt is present, the CPU accepts only the first unmasked enabled interrupt: after that, all other interrupts are ignored regardless of their intrinsic priorities.

3- When the CPU is not in T(halt) or T(hold):

1. It internally latches the HOLD line only during CLK = 1 of the last state before T3(T 2 or T WAIT) and during CLK = ·1 of the previous state before T5 (T4 of a six T-state M1). If the internal latched HOLD signal is high during the next CLK = 1, the CPU will enter T(hold) after the following clock
2. It will internally latch the state of the Unmasked interrupts only during CLK of the next to the last state before each M1 • T1.

Ref. – (1)http://www.bitsavers.org/components/intel/MCS80/MCS80_85_Users_Manual_Jan83.pdf (Page no. 40)

(2) Microprocessor System, Page Number 28

Answer 3

It should depend on when both requests come. Since DMA access bus by cycle stealing(or between cycles) and interrupts are checked before fetching a new instruction, DMA has an upper hand here. Also DMA requires only bus and not CPU, whereas an interrupt may require both. So in case an instruction is being executed, DMA will get its bus first. In case: "before fetching a new instruction", anyone's request could get satisfied first. Plus, this case might also depend on implementation of the microprocessor.

Comments

Thank you for the response..

"It should depend on when both requests come." I think it is given that both requests arrive simultaneously.

I strongly agree with your statement :-

"Interrupts are checked before fetching a new instruction, DMA has an upper hand here."

my reason is :- interrupt signal can come anytime during the interrupt cycle but it is served at the end of instruction cycle but in DMA , BUS is granted at anytime during instruction cycle(Fetch/Decode/operand fetch/execution/write back) using bus grant signal. so , DMA should be preferred here.

one another advantage in DMA is that we have to initialize and terminate once. ie it has only one initialization and ending phase .

please correct me if I m wrong somewhere.

also please explain this statement :- "this case might also depend on implementation of the microprocessor."

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You are correct. If we have to choose from True or False, then it would be True. But for interviews, we should explain it.

 "this case might also depend on implementation of the microprocessor."

By this I mean in the second case, when both DMA request and interrupt arrive before fetching a new instruction an implementer can decide what to do. For example:

1. DMA and interrupt both requires only bus. Then implementer could give higher priority to either DMA or interrupt, so that atleast one's request is satisfied. Also depending on the type of interrupt, priorities can be intermingled with DMA.

2. Interrupt requires both CPU and bus. Then we could serve request of DMA first since it would be faster instead of giving interrupt both things first. Whereas, if interrupt requires CPU first then bus. Then we could serve requests of both, interrupt and DMA, at the same time.

A few more cases like these could also be generated. I hope you got my point here.

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got it..thanks !