GATE CSE 2003 | Question: 10, ISRO-DEC2017-41

Question

For a pipelined CPU with a single ALU, consider the following situations

1. The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand

2. The execution of a conditional jump instruction

3. The $j^{th}$ and ${j+1}^{st}$ instructions require the ALU at the same time.

Which of the above can cause a hazard

• A. I and II only
• B. II and III only
• C. III only
• D. All the three

Answer 1

1. Data hazard
2. Control hazard
3. Structural hazard as only one ALU is there

So, $(D)$. 

https://web.archive.org/web/20120106063906/http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/hazards.html

Comments

@swami_9

Yes you are right

Take I(j) : MUL R1,R2,R3

I(j+1): ADD R5,R6,R7

Now ADD takes one cycle and MUL takes 3 cycles

Then I(j+1) willl have some stalls.

Whatever be the method you are using.

---

Yes in case of “Which of the above must cause a hazard? ”, then because of operand forwarding Statement,I will be false.

Branch hazard can be removed using branch prediction/ pipeline bubbling /etc, this makes Statement II false.

Statement III will always cause Structural hazard ( both accessing same resource).

So, option C will be the correct answer.

---

One Important catch here:

1. The j+1st instruction uses the result of the jth instruction as an operand

We must not assume that operand forwarding is done.

It actually means instructions sequence has something like:

r1 ← r2 + r3

r5 ← r1-r4

This can cause a hazard unless operand forwarding is used.

question clear asks

Which of the above can cause a hazard

So, yes it can cause a hazard. Hope this helps!

Answer 2

Answer is D

I . Read before write (data hazard)

II. control hazard

III. Structural hazard.

Comments

the point number 1, that’s a RAW (Read after Write Hazard) my dear.

Answer 3

https://www.geeksforgeeks.org/gate-gate-cs-2003-question-10/

Answer 4

 

1. Data Hazard (Read After Write - RAW):

   • Situation: The j + 1-st instruction uses the result of the j-th instruction as an operand.
   • Hazard: If the result of the j-th instruction is not yet available in the pipeline when the j + 1-st instruction needs it, a data hazard occurs. This is also known as a read-after-write hazard.

2. Control Hazard (Conditional Jump):

   • Situation: The execution of a conditional jump instruction.
   • Hazard: When a conditional jump instruction is encountered, the pipeline may have to stall until the condition is evaluated and the target address is determined. This is a control hazard, as the flow of instructions is altered based on a condition.

3. Structural Hazard (ALU Usage Conflict):

   • Situation: The j-th and j + 1-st instructions require the ALU at the same time.
   • Hazard: If the pipeline does not have the capability to handle multiple instructions requiring the ALU simultaneously, a structural hazard occurs. This situation is also known as a resource conflict.

therefore the correct answer is D, all can cause hazards